coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-12-09	soc/amd/mendocino: Enable LPC SPI DMA	Karthikeyan Ramasubramanian
2022-11-21	soc/amd/mendocino: Increase CBFS_MCACHE size	Karthikeyan Ramasubramanian
2022-11-14	arch/x86/Kconfig: Move AMD stages arch to common code	Arthur Heymans
2022-11-07	soc/amd/mendocino: Enable x86 SHA accelerator	Karthikeyan Ramasubramanian
2022-11-04	soc/amd: Specify memory types supported by each chip	Martin Roth
2022-10-28	soc/amd/mendocino: Add code for printing STB to boot log	Martin Roth
2022-10-26	soc/amd/mendocino: Enable GPP clk req disabling for disabled devices	Robert Zieba
2022-10-14	soc/amd: factor out common eMMC code	Felix Held
2022-10-07	soc/amd/{CZN,MDN,PCO}: Fix building with only single RW region	Matt DeVillier
2022-09-14	soc/amd/mendocino: Add support for separate RW A/B partition SPL file	Felix Held
2022-09-12	soc/amd: Refactor DPTC Tablet Mode	Tim Van Patten
2022-09-07	soc/amd/mendocino/Kconfig: Enable APOB_HASH	Fred Reitberger
2022-08-31	soc/amd/mendocino/Kconfig: select extended eSPI decode range support	Felix Held
2022-08-18	soc/amd/mendocino: enable CPPC feature	Felix Held
2022-08-12	soc/amd/mendocino: clear Port80 enable bit in ESPI Decode	Jon Murphy
2022-08-11	treewide: Rename Sabrina to Mendocino	Jon Murphy