coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-10-12	soc/amd/genoa/include/data_fabric: add VGA decode enable register	Felix Held
	Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf4a1fd61ad1d545b1ea0ab3fcf6c7a3d0260cd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-10-11	soc/amd/genoa/include: add data_fabric.h	Felix Held
	Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18871af0a8dbc1423524b681d516476e63b9596a Reviewed-on: https://review.coreboot.org/c/coreboot/+/78306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-10-11	soc/amd/genoa: Enable uart	Varshit Pandya
	Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76507 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-10-11	soc/amd/genoa: Add SMI support	Varshit Pandya
	Add SMI definitions as per Genoa PPR Doc #55901 Change-Id: I491f4075cef8976e4b0762752c9e2e3c2ef886d5 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-11	soc/amd/genoa: Add GPIO definitions	Varshit Pandya
	Add GPIO definitions as per Genoa PPR Doc #55901 Change-Id: I0c4e425699c9a158ca95a1baf94f7756f0b12b44 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-10-10	soc/amd/genoa: Enable eSPI early	Arthur Heymans
	Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4965eac4ec3d600b1e840affce4e5b4fa2ea4360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-10-10	soc/amd/genoa: Add aoac.c & enable AOAC devices early	Arthur Heymans
	Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic9553e6016c92c9b1678c395cd6a9e6860bf8a76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76506 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-28	soc/amd/genoa/southbridge.h: Add PM related macros	Arthur Heymans
	All verified with PPR. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: If288079310ba74333f04173978f6a123ce95f4d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-09-28	soc/amd/genoa: Add timer & tsc support	Arthur Heymans
	Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Change-Id: Ie1ae2ba4d4833570ca0621023bdeed67ccabe5cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/76501 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01	soc/amd/genoa: Add minimal viable code for compilation	Arthur Heymans
	This adds a dummy soc (genoa) based on EXAMPLE_MIN86 with amd linker script hooked up. Default to 64bit code as that will be a sensible default for this platform (high memory access required for RAS setup). Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I69253466084d17c4359d7e824d69f12490b076e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76495 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>