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2021-04-05soc/amd/common: Add some ESPI register definitionsMartin Roth
Use definitions instead of magic numbers clean up some whitespace while I'm here. BUG=b:183207262 TEST=Build Change-Id: Ieae53b12e5303641fb3f180c47468aaa6906e9af Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-05soc/amd: Make espi_clear_decodes privateRaul E Rangel
espi_setup already clears most of the controller registers. So this change consolidates the clear logic into one spot. This shouldn't result in a behavior change on Picasso. Picasso already has the eSPI decodes clear on boot, so this change is a nop. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd: Make espi_configure_decodes privateRaul E Rangel
This is only ever called after espi_setup. 55861 - AMD System Peripheral Bus Overview also says that io ranges should be configured before enabling the BUS_MASTER bit. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common/espi: Clear DNCMD_COMPLETE on completionRaul E Rangel
Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0. BUG=b:183524609 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I950cfb81521e35758c120a482670cfdb924201d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common/espi: Reset eSPI registers to known stateRaul E Rangel
This sets the eSPI registers to the reset values specified in the PPR. On Cezanne, the PSP modifies these registers such that the eSPI peripheral cannot send DEFER packets. This causes random bus errors. These reset values are identical to what is currently used on Zork. I didn't clear out ESPI_DECODE because it's currently being done by cb:51749. BUG=b:183524609 TEST=Boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common/espi: Add missing eSPI register definitionsRaul E Rangel
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7e601f767327e0a24a086146623af039388b2e7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05soc/amd/common/espi: Add ESPI_ prefix to SLAVE0_INT_ENRaul E Rangel
This matches the other register definitions. BUG=b:183524609 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0ed92add633f294f92c6a0dde32851d01b10db3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-05soc/amd/common: Add func to clear eSPI IO & memory decode rangesMartin Roth
Previously, the eSPI code would only add to existing decode ranges, and there wasn't any way to clear ranges. This clears all the ranges so the eSPI configuration can start fresh. BUG=b:183207262, b:183974365 TEST=Verify on Guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-31soc/amd/common/block/graphics: Don't add VBIOS to cbmem when using GOPRaul E Rangel
pci_rom_ssdt reloads the oprom from cbfs. It then places it into cbmem and writes the offsets as the ROM ACPI node. The GOP driver modifies the VBIOS so we don't want to reread from cbfs. When using GOP we also pass the offsets with the VFCT table. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaf53e750564f1f0e115cd354790da62e672d74b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-29soc/amd: smbus: Use correct type for uintptr_tPaul Menzel
Fix the format warning below by using `PRIxPTR`, which is defined as unsigned long. src/soc/amd/common/block/smbus/smbus.c:33:56: error: format specifies type 'size_t' (aka 'unsigned int') but the argument has type 'uintptr_t' (aka 'unsigned long') [-Werror,-Wformat] printk(BIOS_ERR, "Invalid SMBus or ASF base %#zx\n", mmio); ~~~~ ^~~~ %#lx src/include/console/console.h:60:61: note: expanded from macro 'printk' #define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args) ~~~ ^~~~ 1 error generated. Change-Id: I727c490d3097dcf36cdbcd4db2852cd49d11785f Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-29soc/amd/common/block/acpimmio/mmio_util: add fch_disable_kb_rstFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie65e39ffb8c353415f5b68e1e0f378d18eeb7498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51784 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-29soc/amd: move PM_RST_CTRL1 register definition to common acpimmio headerFelix Held
TEST=Verified that this register and the defined bits exist in Cezanne, Picasso, Stoneyridge, Bolton and SB800. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28soc/amd/common/gpio: add PAD_NF_SCI pad typeFelix Held
This patch adds a pin configuration macro that supports both switching a pin to its native function and configuring it as a SCI source. This is a preparation to remove the GPIO2 soc_gpio_hook. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If0da5c010f35fd902f6b8857368daec93c12394a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50373 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/amd/common/block/i2c: Use `size_t` for `num_pins`Angel Pons
There's no need to use a fixed-width type here. Change-Id: I727c64661990040db356c5508fecc0a65960c095 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51794 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28soc/amd/common/block/i2c: Fix printf format specifiersAngel Pons
The correct printf format specifier for an `unsigned int` is `%u`. Change-Id: Iaf780eb366f8c3493b89beb9a5643fa285e7825d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51793 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25soc/amd/common/block/i2c: fix control flow bugFelix Held
commit 4f87ae1d4a3a597f1260534001bd99160cc8ca99 introduced a regression in the I2C initialization resulting in soc_i2c_misc_init never getting called, since the continue statement was indented like it belonged to the if above, but due to the missing curly braces it was outside the if block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Found-by: Coverity CID 1451395, 1451387 Change-Id: Id1f17ad59cba44e96881f5511df303ae90841ab3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51786 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25soc/amd/common/block/gpio_defs: Wake from either S0i3 or S3Karthikeyan Ramasubramanian
Add a helper bit mask to enable wake from either S0i3 or S3. BUG=None TEST=Build the Guyrbush mainboard. Change-Id: I934abad78135260081a61aee4c496b362e483de1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-23soc/amd/common/block/gpio_defs: Support wake and debounce configurationKarthikeyan Ramasubramanian
Add a pad configuration macro to support configuring both wake and debounce. This support is required by Pen Detect GPIO. BUG=b:180539900 TEST=Build Guybrush mainboard. Change-Id: I3343a4e80fd5aa3047d76ff9f91ea57c3763bbca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-22soc/amd/common/block/psp/psp: update psp_status_nobase error messageFelix Held
When the soc_get_mbox_address functions returns 0 after not being able to find an initialized PSP base address MSR or in case of Stoneyridge the PSP's BAR3, the code will print an error string. This string needs to reference both PSP_ADDR_MSR and PSP BAR3 and not only the latter one, since in Picasso and Cezanne only the former one is present. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32a1e87e2a7d89c7b53f47c987e7bf0556154cf7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-22acpi/acpigen.h: Add more intuitive AML package closing functionsJakub Czapiga
Until now every AML package had to be closed using acpigen_pop_len(). This commit introduces set of package closing functions corresponding with their opening function names. For example acpigen_write_if() opens if-statement package, acpigen_write_if_end() closes it. Now acpigen_write_else() closes previously opened acpigen_write_if(), so acpigen_pop_len() is not required before it. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-22soc/amd/common/block/i2c: Move SoC agnostic parts into commonKarthikeyan Ramasubramanian
The logic behind I2C bus initialization, I2C MMIO base address getter and setter, I2C bus ACPI name resolution are identical for all the AMD SoCs. Hence moving all the SoC agnotic parts of the driver into the common driver and just configure the SoC specific parts into individual I2C drivers. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. Verify some I2C peripheral functionality like trackpad and touchscreen. Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22soc/amd/common: Introduce I2C driver common to all AMD SoCsKarthikeyan Ramasubramanian
I2C driver is replicated in each generation of AMD SoCs. Introduce a common I2C driver that can be used across all the AMD SoCs. To begin with, peripheral reset functionality is moved into this common driver. SoC specific I2C driver passes the SCL pin configuration in order for the common driver to reset the peripherals. More functionality can be moved here in subsequent changes. Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as an effort towards using inclusive language. BUG=None TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C peripherals are detected as earlier in Dalboz. localhost ~ # i2cdetect -y 0 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- -- 60: 70: localhost ~ # i2cdetect -y 1 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-18soc/amd/common: Make fch_spi_config_modes staticMathew King
It is currently only used in this translation unit. Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Ib779a38306fb45320f3e4eb71f63630023d59906 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51535 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17amd: refcode_loader: Switch to new CBFS APIJulius Werner
This patch rewrites some parts of the Agesa refcode loader to eliminate the passing of raw rdevs between functions, so that we can get rid of cbfs_boot_locate() in favor of more high-level APIs. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I2a6e1158ed7425c69c214462bc52e8694a69997a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Replace more instances of cbfs_boot_locate() with newer APIsJulius Werner
In pursuit of the eventual goal of removing cbfs_boot_locate() (and direct rdev access) from CBFS APIs, this patch replaces all remaining "simple" uses of the function call that can easily be replaced by the newer APIs (like cbfs_load() or cbfs_map()). Some cases of cbfs_boot_locate() remain that will be more complicated to solve. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Icd0f21e2fa49c7cc834523578b7b45b5482cb1a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17cbfs: Move stage header into a CBFS attributeJulius Werner
The CBFS stage header is part of the file data (not the header) from CBFS's point of view, which is problematic for verification: in pre-RAM environments, there's usually not enough scratch space in CBFS_CACHE to load the full stage into memory, so it must be directly loaded into its final destination. However, that destination is decided from reading the stage header. There's no way we can verify the stage header without loading the whole file and we can't load the file without trusting the information in the stage header. To solve this problem, this patch changes the CBFS stage format to move the stage header out of the file contents and into a separate CBFS attribute. Attributes are part of the metadata, so they have already been verified before the file is loaded. Since CBFS stages are generally only meant to be used by coreboot itself and the coreboot build system builds cbfstool and all stages together in one go, maintaining backwards-compatibility should not be necessary. An older version of coreboot will build the old version of cbfstool and a newer version of coreboot will build the new version of cbfstool before using it to add stages to the final image, thus cbfstool and coreboot's stage loader should stay in sync. This only causes problems when someone stashes away a copy of cbfstool somewhere and later uses it to try to extract stages from a coreboot image built from a different revision... a debugging use-case that is hopefully rare enough that affected users can manually deal with finding a matching version of cbfstool. The SELF (payload) format, on the other hand, is designed to be used for binaries outside of coreboot that may use independent build systems and are more likely to be added with a potentially stale copy of cbfstool, so it would be more problematic to make a similar change for SELFs. It is not necessary for verification either, since they're usually only used in post-RAM environments and selfload() already maps SELFs to CBFS_CACHE before loading them to their final destination anyway (so they can be hashed at that time). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I8471ad7494b07599e24e82b81e507fcafbad808a Reviewed-on: https://review.coreboot.org/c/coreboot/+/46484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17program_loading: Replace prog_rdev() with raw start pointer and sizeJulius Werner
Since prog_locate() was eliminated, prog_rdev() only ever represents the loaded program in memory now. Using the rdev API for this is unnecessary if we know that the "device" is always just memory. This patch changes it to be represented by a simple pointer and size. Since some code still really wants this to be an rdev, introduce a prog_chain_rdev() helper to translate back to that if necessary. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If7c0f1c5698fa0c326e23c553ea0fe928b25d202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-16cbfs: Remove prog_locate() for stages and rmodulesJulius Werner
This patch removes the prog_locate() step for stages and rmodules. Instead, the stage and rmodule loading functions will now perform the locate step directly together with the actual loading. The long-term goal of this is to eliminate prog_locate() (and the rdev member in struct prog that it fills) completely in order to make CBFS verification code safer and its security guarantees easier to follow. prog_locate() is the main remaining use case where a raw rdev of CBFS file data "leaks" out of cbfs.c into other code, and that other code needs to manually make sure that the contents of the rdev get verified during loading. By eliminating this step and moving all code that directly deals with file data into cbfs.c, we can concentrate the code that needs to worry about file data hashing (and needs access to cbfs_private.h APIs) into one file, making it easier to keep track of and reason about. This patch is the first step of this move, later patches will do the same for SELFs and other program types. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13soc/amd/common/block/graphics/graphics: GOP: load VBIOSNikolai Vyssotski
Load VBIOS in pci set_resources to PCI_VGA_RAM_IMAGE_START (0xc0000) since pci_dev_init() will not load it in GOP case (VGA_ROM_RUN is not set). Add Cezanne GFX PID. BUG=b:171234996 BRANCH=Zork Change-Id: I4a6fea9b6cd60c862e15ed2ed539869c0f9bd363 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-12soc/amd/common/amdblocks/chip.h,psp.h: add missing stdint.h includeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6fb53d88a840a782af7502660ff85205f84523b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12soc/amd/common/amdblocks/smi.h: include types.h instead of stdint.hFelix Held
gpe_configure_sci has a size_t type parameter, so we need to include types.h instead of stdint.h here. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2879d5cf27c432871a2b9c5c90bdd539b97f9d3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12soc/amd/common/block/smu: rename mailbox register definesFelix Held
Since we have the SMN access block now, rename the SMU mailbox interface registers to clarify that those are in the SMN register space. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-12soc/amd/common: factor out SMN access function from SMU codeFelix Held
The SMU mailbox interface gets accessed over the SMN register space, so factor out those access functions into a separate common code SMN access building block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iabac181972c02ae641da99f47b2aa9aa28dae333 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-11soc/amd: move warm reset flag function prototypes to common codeFelix Held
Even though the implementation is different on Stoneyridge compared to Picasso and Cezanne, the function prototypes are identical, so move them to the AMD SoC common reset header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-10soc/amd/common/block/graphics/graphics: GOP: implement vbt_get()Nikolai Vyssotski
Even though AMD does not need VBT we still need to implement the vbt_get() function to not break the build with GOP driver enabled (see fsps_return_value_handler() in fsp2_0/silicon_init.c BUG=b:171234996 BRANCH=Zork Change-Id: I80a5131a9852a05998b55b847243748d24cf535f Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-10soc/amd/*/smihandler: factor out ELOG and SMMSTORE handlerFelix Held
This also replaces the southbridge_ prefix of the handler functions with a handle_ prefix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib6ea1f4e2700c508a8bf72c488043e276ba4a062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51354 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08soc/amd,mb/google/,mb/amd: Move sleepstates.aslRaul E Rangel
This file is common for all the AMD platforms. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08soc/amd/common: Move GEVENT definitions to gpio_defs.hMathew King
This change will allow for GEVENTs to be used in ASL code. BUG=b:180507937 TEST=builds Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I77abd134555c21a32a302ee92cd080284cd2e634 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-08soc/amd/common/block/graphics/graphics: report GOP frame bufferNikolai Vyssotski
GOP needs to register the new framebuffer. BUG=b:171234996 BRANCH=Zork Change-Id: I17b6533520b0628df9529d09f70d5fc28339d522 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-06soc/amd/picasso: move APOB NV cache to common codeFelix Held
Also rename mrc_cache to apob_cache. BUG=b:181766974 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4877b05443452c7409006c1656e9d574e93150a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-02soc/amd/common/blocks/lpc: Explicitly disable serial IRQRaul E Rangel
The serirq enable bit defaults to true, so if we want it disabled, we need to explicitly disable it. BUG=b:180631748 TEST=Boot majolica and see spurious IRQ 9 gone. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f1e18f836f29cb75334dd88c91ad047f5bdfb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-03-01soc/amd/common/block/acpimmio: Add fch_disable_legacy_dma_ioRaul E Rangel
Add a method to disable decoding the legacy DMA IO ports. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I979445cfa8317334e62e9ebf12256ece9f8058bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/51075 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22soc/amd: Move root complex SSDT TOM1/TOM2 generation functionRaul E Rangel
This will also be used for cezanne. Stoney also has a similar function, but it hard codes the scope path. I didn't have a device setup to test if switching to this function was a no-op. So I left it. TOM2 isn't used by any ASL, so we could remove it later. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-19soc/amd/common/block/data_fabric: add warning about broadcast readsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If1b65ae3dd2b5c8fe7bc29a267d108e4d3a3e567 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50883 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19soc/amd: move SMM finalization to common codeFelix Held
This adds the SMM finalization to Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1a2b433d92df2a76979e2e6a3d1dde996303ba78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50801 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19include/cpu/amd/msr: rename MSR_PSP_ADDR to PSP_ADDR_MSRFelix Held
The new name is more consistent with the rest of the MSR definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5666d9837c61881639b5f292553a728e49c5ceb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50855 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19soc/amd/common/amdblocks/psp: move MSR_PSP_ADDR to include/cpu/amd/msr.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5bd6f74bc0fbe461fa01d3baa63612eaec77b97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50854 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-19memlayout: Store region sizes as separate symbolsJulius Werner
This patch changes the memlayout macro infrastructure so that the size of a region "xxx" (i.e. the distance between the symbols _xxx and _exxx) is stored in a separate _xxx_size symbol. This has the advantage that region sizes can be used inside static initializers, and also saves an extra subtraction at runtime. Since linker symbols can only be treated as addresses (not as raw integers) by C, retain the REGION_SIZE() accessor macro to hide the necessary typecast. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ifd89708ca9bd3937d0db7308959231106a6aa373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-02-18soc/amd/common/block/data_fabric: fix data_fabric_write32 broadcast caseFelix Held
Calling data_fabric_write32 with BROADCAST_FABRIC_ID as instance_id would have caused an infinite recursion, so call the right function data_fabric_broadcast_write32 for that case instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7f0a80f0430e8bfb29ee510ef86c278e3a42063 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-18Revert "soc/amd: Add option to select if SOC supports ESPI sub decode"Felix Held
This reverts commit 64d0ad347b5c9c698547f0ff15779e88a10014f4. In the current revision 3.001 of the PPR #56569 the register exists and the bit definitions match. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie7a97843c3dac897f79f229b660b7e30b34eef93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-18soc/amd/common/block/iommu: move ACPI name to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0f1dce92475ce0ee05a8d090fc3b3d1e613f62c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50821 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/amd/common/block/smbus: move ACPI name to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I47415be02571240d3cecfdb91cb9f8097c5b7fde Reviewed-on: https://review.coreboot.org/c/coreboot/+/50819 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-18soc/amd/common/block/lpc: move ACPI name to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7517d81d41422cfa10fabd12ab3da4f61c3f9034 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50818 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-17soc/amd/picasso/uart: move uart_inject_ssdt to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic033fc2817d44ff873f93a45e069c0e8aa0be99f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-16soc/amd/common/*/Kconfig: remove unneeded default n for bool optionsFelix Held
n is the default of bool Kconfig options, so no need to have that added to each option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8775d84caee6fda95eb7749e96090fe05417e764 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50779 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16soc/amd: Move aoac.asl from picasso into commonRaul E Rangel
I also removed the unnecessary #include in soc.asl. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifbd79871fd49b18f45d97f64ccd68fa96eaaebce Reviewed-on: https://review.coreboot.org/c/coreboot/+/50572 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-16ACPI: Add acpi_reset_gnvs_for_wake()Kyösti Mälkki
With chipset_power_state filled in romstage CBMEM hooks and GNVS allocated early in ramstage, GNVS wake source is now also filled for normal boot path. Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-02-14soc/amd/common/block/data_fabric: add data_fabric_print_mmio_confFelix Held
Output on Picasso at the beginning of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 93 fc00 febf 1 93 1000000 ffffffff 2 93 d000 f7ff 3 90 0 0 4 93 fed0 fed0 5 90 0 0 6 90 0 0 7 90 0 0 Output on Picasso at the end of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 93 fc00 febf 1 93 1000000 ffffffff 2 93 d000 f7ff 3 1093 fed0 fedf 4 90 0 0 5 90 0 0 6 90 0 0 7 90 0 0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I74617dfc6099489f3c81d0e385b502f1bbecea78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50640 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/picasso/data_fabric: factor out common MMIO register definesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I663a73308d33f48c6b945007f3eaac84d4712f59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50639 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/picasso/data_fabric: move more helper functions to common codeFelix Held
The number of data fabric MMIO registers is SoC-specific, so we need to keep that in the SoC code. This also removes a redundant pair of brackets and moves a loop counter declaration into the head of the loop. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8499f1c1f7bf6849b5955a463de2e06962d5de68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50638 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/common/block/data_fabric: add data_fabric_broadcast_read/write32Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I81e7ff293865ef22ed74606e1e79f67a460de4a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50621 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/common/block/data_fabric: add data_fabric_write32Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9c1ae03e9aec1dec45333e697060308cb6cbda4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/50620 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/picasso: move data_fabric_read32 to common codeFelix Held
The exact same mechanism is used on Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-14soc/amd/cezanne: Fill FADT and MADTRaul E Rangel
The MADT doesn't populate the IO-APICs yet since we need FSP to configure those. The FADT differs from picasso in the following ways: * The duty_offset is supposed to be 0 * Don't clear x_firmware_ctl_l * Make the extended addresses use MMIO Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib6c3a01084a0de33894885b47c637a292d252ed4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-14soc/amd: Move update_microcode.c to common/block/cpuRaul E Rangel
We also want to support uCode loading on cezanne. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-13soc/amd/common/acpi/gpio_bank_lib.asl: Add missing headerRaul E Rangel
This file references ACPIMMIO_GPIO0_BASE. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic65a1f8759d10e7d78e30cfc82895e5af8cd83a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50571 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-13soc/amd: introduce and use common IOAPIC IDsFelix Held
Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as IOAPIC IDs and Picasso had Kconfig options to configure that, but still used the common SMBus controller code that used CONFIG_MAX_CPUS as ID for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a mismatch between the ID that gets written into the FCH IOAPIC register and the ID in the corresponding ACPI table. In order to avoid that add defines to each SOC's southbridge.c and use them in all soc/amd code. Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12soc/amd: add and use fch_enable_hpet_decodeFelix Held
On Picasso we missed setting this bit in coreboot and since the default after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge and Cezanne have the HPET decode enable bit in the same position in the same register. In the ACPI table entry written by southbridge_write_acpi_tables the HPET entry gets added, so we should make sure that we enable the decode. TEST=HPET still works on Mandolin. Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50512 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12soc/amd/common: add and use fch_enable_ioapic_decodeFelix Held
The default value of this bit is 0, so set it right before calling setup_ioapic to make sure that it's set and not to have to rely on FSP doing the right thing. Change-Id: Ife886451a6927965769282fc5644c2085abb9585 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50513 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12soc/amd: Move MADT IRQ override settings into common_configRaul E Rangel
This is another common ACPI setting. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iefecabae1d83996a9a4aaadd2a53c2432441e1b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50558 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12soc/amd: Move fadt device tree settings into common_configRaul E Rangel
This is ACPI specific config that applies to all the AMD SoCs. Stoney doesn't currently use this, but we can add that functionality later. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12soc/amd: Move acpi_fill_mcfg into common/blocks/acpiRaul E Rangel
This is common between stoney, picasso, and cezanne. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5fb40e8c6817773212c5fbd66c5c06bd2bae1eda Reviewed-on: https://review.coreboot.org/c/coreboot/+/50556 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12soc/amd: Move southbridge_write_acpi_tablesRaul E Rangel
This is common between all the chipsets. It's also required by common/block/lpc/lpc.c. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12soc/amd/picasso: move bert_reserved_region to common/block/cpu/noncarFelix Held
The same functionality will eventually be needed on Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12soc/amd: select ACPI_AMD_HARDWARE_SLEEP_VALUES in common ACPI codeFelix Held
Change-Id: Ib03c6799017c9f51f3ffac8400c85675ac5d63f1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-12soc/amd/picasso/psp: move to common code and rename to psp_smm_gen2Felix Held
Change-Id: I771a7d36eea7307754386824190624a09c0e38f7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-11soc/amd/common/block/acpi/pm_state: don't rely on undefined behaviorFelix Held
Change-Id: I5a76a38f8d84666f6b9c0bfffecca064fa82d593 Found-by: Coverity CID 1445994 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-11soc/amd/common: Fix missing header in amd_pci_utils.hRaul E Rangel
This was causing a build error because size_t wasn't defined. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia467c7d6cc0f71580d0b323cb560c444d53bd7f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-11soc/amd: fully commonize clear_tvalidFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50466 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd: include cpu/x86/smm directory in common SMM MakefileFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50464 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd: move southbridge_smi_handler to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I650498321736eee3d33af51216eda1b650f11744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50463 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd: factor out common SMM relocation codeFelix Held
The common code gets moved to soc/amd/common/block/cpu/smm, since it is related to the CPU cores and soc/amd/common/block/smi is about the SMI/ SCI functionality in the FCH part. Also relocation_handler gets renamed to smm_relocation_handler to keep it clear what it does, since it got moved to another compilation unit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd*/smihandler: factor out and rename clear_smi_sci_statusFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd6c3bebee1ccf7e7e7987d8ae3d9fa654019791 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50460 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11soc/amd*/smihandler: factor out and rename clear_all_smi_statusFelix Held
The old name was misleading, since it doesn't disable the generation of SMIs, but clears the status registers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/common/psp_gen2: print error for uninitialized MSR_PSP_ADDRFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b6362a9eb2344293dad22357651f646774af789 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50448 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd/common/block/psp: factor out soc_get_psp_base_addressFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-10soc/amd/common/blocks/lpc: Remove common SPI registersRaul E Rangel
Use the SoC versions instead. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/common/block: Fix guards for PSP transfer bufferRaul E Rangel
The transfer buffer is only required when using VBOOT_STARTS_BEFORE_BOOTBLOCK. The VBOOT workbuffer is only required when VBOOT_STARTS_BEFORE_BOOTBLOCK or VBOOT_STARTS_IN_BOOTBLOCK. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10soc/amd/common/block/cpu/noncar: Remove unneeded whitespace before tabElyes HAOUAS
Change-Id: Ib88358ca26876cd25247cd9619fb2b70f6859ac2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10soc/amd/block/psp/psp: raise log level of PSP failure messagesFelix Held
If the PSP didn't like a command this should be at least a warning on the console and not just a debug message. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7e5f6320631cca86813e98f82b8c0c21bf18af1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10soc/amd: Move southbridge_smi_set_eos to common/blocks/smi/smi_utilFelix Held
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I69466143315c1c9870a97c9ef8f68ed85f38e779 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50415 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd: Move global_smi_enable to common/blocks/smi/smi_utilFelix Held
Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42989 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10soc/amd: Move soc_route_sci to common/blocks/smi/smi_utilFelix Held
Change-Id: Ic379723c0bf6e5edf5f3d63cc11b24d0e59b5075 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42988 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09soc/amd/picasso/cpu: move set_cstate_io_addr to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b8a38ea39d8dc56ff1249a3212fe352b3e805ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/50407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09soc/amd/picasso/cpu: move get_cpu_count to common codeFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0690787f492d764a20a4219822eb10fb5cd86de0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-09soc/amd/picasso: move smm_region to soc/amd/common/block/cpu/noncarFelix Held
The same functionality is needed on Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-09src: Add missing <cbmem.h>Elyes HAOUAS
Change-Id: I75a816c594b326df8a4aa5458bb055fca35e1741 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-08soc/amd/common/memmap: add comment about types in memmap_early_dramFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I295bfcb05571492adbe81ffc579a835be4abffe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-07src: Remove redundant include <rules.h>Elyes HAOUAS
Change-Id: Ie4692246d059734bb5bad6c64042b64068636ab6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-07soc/amd/picasso: Move memmap_early_dram to common blocksRaul E Rangel
We need the same functionality for cezanne. TEST=Boot ezknil Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0800c662bb473eb571c74e76a8247298f534b53f Reviewed-on: https://review.coreboot.org/c/coreboot/+/50337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-06 23:31:25 +0000