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2022-01-12soc/amd/common/block: add new PCI IDs to common codeFelix Held
The existing common AMD SoC code supports some of AMD Family 17h Model A0h SoC's PCI devices that however have different PCI IDs. Add the new PCI ID defines to the PCI ID lists of the common PCI drivers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I50960e502c63a2ffcfed35178c5e7c9729ef061e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-10src/soc: Remove unused <stdlib.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l 'memalign(\|malloc(\|calloc(\|free(' -- src/) Change-Id: I08e1a680de9bfcc7d74e88a15abe9eef327b4961 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-01-10src/soc/amd: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Iff7fdd679ac31a121d56746ed8efa1b3da932638 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/soc/amd: Remove unused <timer.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <timer.h>' -- src/) <(git grep -l 'NSECS_PER_SEC\|USECS_PER_SEC\|MSECS_PER_SEC\|USECS_PER_MSEC\|mono_time\|microseconds\|timeout_callback\|expiration\|timer_monotonic_get\|timers_run\|timer_sched_callback\|mono_time_set_usecs\|mono_time_set_msecs\|mono_time_add_usecs\|mono_time_add_msecs\|mono_time_cmp\|mono_time_after\|mono_time_before\|mono_time_diff_microseconds\|stopwatch\|stopwatch_init\|stopwatch_init_usecs_expire\|stopwatch_init_msecs_expire\|stopwatch_tick\|stopwatch_expired\|stopwatch_wait_until_expired\|stopwatch_duration_usecs\|stopwatch_duration_msecs\|wait_us\|wait_ms' -- src/) Change-Id: I581f446330c4e99c587938d4eab387a51e3961e0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-10src/soc/amd: Remove unused <acpi/acpi.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: I810f6c78a070da554a65914e94b13e354f97f995 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-07soc/amd/common/block/include/lpc: add comment about RANGE_UNIT valuesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22f3485ec81f76af7e0e96b7c1271d5ccf52e701 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-07soc/amd/common/lpc/espi_util: move register definitions to header fileFelix Held
Define the register offsets and bits in a separate header file instead of in the middle of the .c file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I814192b2dfeff05877ac857dd89e8cdc7ae5ee25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-07soc/amd/common/block/espi: use lower case hex digits in definitionsFelix Held
coreboot uses lower case hex digits instead of upper case ones. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0955db7afd101ab522845d5911ff971408e520e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60769 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-07soc/amd/common/lpc/espi_util: handle espi_get_configuration errorFelix Held
In espi_wait_channel_ready the return value of espi_get_configuration didn't get checked before. In the case of the espi_send_command call in espi_get_configuration returning CB_ERR, espi_get_configuration didn't write to the local config variable, so if this happens in the first pass of the do-while loop, the following espi_slave_is_channel_ready call would use the uninitialized local config variable as parameter. Fix this by checking the return value of espi_get_configuration. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iff1a0670e17b9d6c6f4daf2ea56badf6c428b8c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-05src/soc/amd: Remove unused <delay.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <delay.h>' -- src/) <(git grep -l 'get_timer_fsb(\|init_timer(\|udelay(\|mdelay(\|delay(' -- src/) |grep "<" Change-Id: Iefb37d28c7f13563fa652cd6b2f661f462a3a32e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-01src: Drop duplicated includesElyes HAOUAS
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-20soc/amd/common/lpc/espi_util: use enum cb_err type for return valuesFelix Held
Use enum cb_err as return type of all remaining functions that only return success or failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6cff8480d99641fdfb613bb3e4edc4055ad5efc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/common/lpc/espi_util: use enum cb_err type for return valuesFelix Held
Use enum cb_err as return type of all functions that aren't exposed outside of this compilation unit. The checks if a function has returned a failure are replaced with checks if the return value isn't CB_SUCCESS which is equivalent if only those two values are used, but also detects a failure if any unexpected value would be returned. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If8c703f62babac31948d0878e91bd31b31bebc01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/common/lpc/espi_util: simplify espi_configure_decodesFelix Held
The intermediate ret variable isn't needed. espi_open_generic_io_window only returns 0 or -1, so if ret is != 0, it has to be -1. This is a preparation to use the enum cb_err type for the return values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia6c7f4cedf8c2defadcf4c4da1697a97c7b401f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20soc/amd/common/lpc/espi_util: simplify espi_get_general_configurationFelix Held
The intermediate ret variable isn't needed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e6747cf468c5ba8da6c1a3b20022851e32ad951 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-18soc/amd/common/block/acpimmio/print_reset_status: add missing status bitFelix Held
Both the Picasso PPR #55570 Rev 3.18 and the Cezanne PPR #56569 Rev 3.03 define bit 9 of the PM_RST_STATUS register as internal Thermal Trip reset status bit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ida8b13fe62b16c18fc9924520b83220e73eca624 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-15soc/amd/common/block/psp: move psp_notify_dram to psp_gen1.cFelix Held
The MBOX_BIOS_CMD_DRAM_INFO PSP mailbox command is only available on the first generation of PSP mailbox interface and not on the second generation. The second generation of the PSP mailbox interface was introduced with the AMD family 17h SoCs on which the DRAM is already initialized before the x86 cores are released from reset. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97b29fdc4a71d6493ec63fa60f580778f026ec0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-15soc/amd/common/block/spi/fch_spi_ctrl: improve printk messagesFelix Held
Replace FCH_SC with FCH SPI in the printk messages to make those a bit clearer and also remove an unneeded line break in another printk call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ff02163e6a48a2cc8b7fe89b15826e154715d29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/block/spi/fch_spi_ctrl: handle failure in execute_commandFelix Held
When wait_for_ready returned a timeout, execute_command still ended up returning success. Fix this be returning a failure in this case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id012e74e26065c12d003793322dcdd448df758b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/block/spi/fch_spi_ctrl: rework dump_stateFelix Held
Introduce and use enum spi_dump_state_phase to indicate from which phase of the SPI transfer dump_state gets called to print the relevant debug information for that phase. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2f54d4a7eb2f3b9756b77a01533f7c99e8597bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/60118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/include/spi: add Cezanne-specific commentFelix Held
The Cezanne PPR #56569 Rev 3.03 has one more SPI FIFO bytes defined compared to the previous generations. It is unclear if adding some special handling for Cezanne would be worth the effort, since the current code just doesn't use the last byte which should be safe to do, since this only affects the maximum number of bytes that can be used for one SPI transaction. Having another byte to use on Cezanne wouldn't reduce the number of SPI transactions to write a 256 byte data block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic730f4fe838f59066120c811833995c132c84c1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/60117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15soc/amd/common/include/spi: fix SPI_FIFO_LAST_BYTE defineFelix Held
The last byte of the SPI FIFO SPI_FIFO_LAST_BYTE is at offset 0xc6 of the SPI controller's MMIO region for Stoneyridge and Picasso. Both SPI_FIFO_LAST_BYTE and SPI_FIFO_DEPTH had an off-by-one error that ended up cancelling out each other, so the resulting value for SPI_FIFO_DEPTH isn't changed. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1676be902ccf57e2e9f69d81251b4315866a0628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-09soc/amd/common/block/psp: add psp_efs.c to build for both PSP GEN1&2Felix Held
The PSP EFS code to get the SPI mode and speed from the amdfw part of the firmware image also works for Stoneyridge which is the one SoC that selects SOC_AMD_COMMON_BLOCK_PSP_GEN1. Also amdblocks/psp_efs.h already handles the SOC_AMD_STONEYRIDGE case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibddd3f9237e561d9f0f6b4ad70f59cce1f956986 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resumeRaul E Rangel
According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware_Specification.html#pm1-event-grouping > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI > only platforms (where SCI_EN is always set), when transitioning from > either the mechanical off (G3) or soft-off state to the G0 working > state this register is cleared prior to entering the G0 working state. This means we don't want to clear the PM1 register on resume. By clearing it the linux kernel can't correctly increment the wake count when the power button is pressed. The AMD platforms implement the _SWS ACPI methods, but the linux kernel doesn't actually use these methods. BUG=b:172021431 TEST=suspend zork and push power button and verify power button wake_count increments. Verified other wake sources still work. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-08soc/amd/common/block/spi: fix setting SPI_USE_SPI100 in SPI100_ENABLEFelix Held
Use a read modify write sequence when setting the SPI_USE_SPI100 bit in the SPI100_ENABLE register. This avoids clearing other bits in the register which might cause instabilities of the SPI interface. The reference code for both Picasso and Cezanne also only sets the SPI_USE_SPI100 bit and doesn't zero out the other bits. TEST=Verified that Mandolin still boots. It didn't show any signs of possibly related instabilities before though, so this test doesn't say much. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71c2ec1729d5cb4cdff6444b637af29caaa6f1c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd/common/block/include/spi: update fch_spi_early_init descriptionFelix Held
commit 90ac882a32075b44435aa19ea664b89b79cac76e (soc/amd/common/block/ spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST) introduced a Kconfig option to enable/disable the 4DW burst support in the SPI flash data prefetcher, but missed to update the documentation above the fch_spi_early_init prototype, so update the outdated documentation now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I07c4b0b02251da63d34a172e2636894e99845d6b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-08soc/amd: use KiB and MiB definitionsFelix Held
Use KiB and MiB instead of multiplying/dividing with/by the numeric value when doing region size calculations. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I56c380190b11aa3214cce31b82974327e3d15000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-11-30soc/amd/stoneyridge/psp: move soc_get_mbox_address to common psp_gen1Felix Held
Despite Stoneyridge being one only SoC in soc/amd that uses the first generation of the PSP mailblox interface, this code is common for all SoCs that use the first PSP mailbox interface generation, so move it to the common PSP generation 1 code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78126cb710a6ee674b58b35c8294685a5965ecd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59701 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-30soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defsFelix Held
Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04, Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29soc/amd/common/block/lpc: use 32 bit accesses in lpc_enable_port80Felix Held
When using 32 bit PCI accesses in lpc_enable_port80, we can use the LPC_IO_OR_MEM_DECODE_ENABLE and DECODE_IO_PORT_ENABLE4 defines and don't need to re-define bits with offsets from the beginning of the third byte within this 32 bit register. This allows to drop the LPC_IO_OR_MEM_DEC_EN_HIGH register definition which points to LPC_IO_OR_MEM_DECODE_ENABLE + 2 and to drop the re-definitions of the bit re-definitions with a different offset. The code in lpc_enable_port80 was originally copied from sb/amd/agesa/ hudson/early_setup.c which might be sort-of a copy from what the AGESA reference code does. TEST=When commenting out SOC_AMD_COMMON_BLOCK_USE_ESPI in the Kconfig of Mandolin and selecting AMD_LPC_DEBUG_CARD, all POST codes still get shown on the POST code LED display when this patch is applied. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I001bb1c2ccf99e36d4fbd73d3bf96b78ddb87d67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29soc/amd/common/block/lpc/lpc_util: drop lpc_enable_pci_port80Felix Held
This function is unused and none of the SoCs using this code has a physical PCI interface any more, so drop this function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia5c5a8ec29264a075fefe75038ef2a84684d6427 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-29src/cpu,soc/amd/common/block/cpu: Add preload_microcodeRaul E Rangel
This will enable preloading the microcode. By preloading the file, into cbfs_cache we reduce boot time. BUG=b:179699789 TEST=Boot guybrush with CL chain and see microcode preloading and a reduction of 1 ms. | 112 - started reading uCode | 1.041 | 1.204 Δ( 0.16, 0.01%) | | 113 - finished reading uCode | 1.365 | 0.011 Δ( -1.35, -0.10%) | Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If0c634c692c97769e71acd1175fc464dc592c356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-29soc/amd/common/block/psp/psp_def: drop PSPV2_STATUS_* definesFelix Held
PSPV2_STATUS_ERROR and PSPV2_STATUS_RECOVERY aren't used and the bit definitions are also wrong, so drop those defines. For the PSP mailbox interface version 2, struct pspv2_mbox is used to access the correct status bits. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e2aadfde00e2f7b0f99b462b8e3d6954959a584 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-25soc/amd/*/data_fabric: use DF_ prefix for bit and shift definesFelix Held
Adding the DP_ prefix to the defines for MMIO_NP, MMIO_WE and MMIO_RE clarifies the scope of those definitions. For consistency also add this prefix to MMIO_DST_FABRIC_ID_SHIFT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a509ccc071aa51a67552fb9e7195358a76fe4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/*/include/data_fabric: make MMIO_NP definition SoC-specificFelix Held
On Picasso the MMIO_NP bit in the D18F0_MMIO_CTRL0 data fabric register is bit 12, but that has changed to bit 16 in Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I64c06b84e2c0737b259077e7932f418306638e19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/aoac: fix typo in FCH_AOAC_REF_CLK_OK_STATE definitionFelix Held
The bit is called REF_CLK_OK_STATE and not RST_CLK_OK_STATE, so change the name of the define to FCH_AOAC_REF_CLK_OK_STATE. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iae26db94d83ebb2cb799f6d3e0bec37c8e849219 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: add missing de-glitching definesFelix Held
There were only definitions for removing low, high or both glitches, but not to not remove glitches, so add this too for completeness. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I650f7754546935539339c02bb6a94bb3f855d4ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/59631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: rework de-glitching definesFelix Held
I found the name of the DEB_GLITCH_NONE definition a bit misleading, so change it to DEB_GLITCH_REMOVE which should clarify what this will do. The description for this value in the PPR/BKDG is "Remove glitch". This also puts the define in line with GPIO_DEB_REMOVE_GLITCH which is the only place where DEB_GLITCH_NONE/DEB_GLITCH_REMOVE is used. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I59648710e0ff28c2026e1b2cc7e433cafb2f2807 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: use tabs for indentationFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibf7482d20c6d27b2314ec8a31c349eb90c8a8feb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/gpio: drop unused gpio_get_addressFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5b47324af368f81288e9e9be65fe0f1ae2fa3697 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: drop unused GPIO_PIN_IN/OUTFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idf00879701b223ecaca74aef2a51a1b86d2c6ce3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: de-duplicate pin status bit defsFelix Held
De-duplicate the definitions for the pin status bit and use this new definition in both the C and the ACPI code. TEST=Timeless build results in identical image for amd/mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b0fe7dbec5dac176cdfa9690862433f202fb552 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: drop duplicate wake bit defsFelix Held
The GPIO_WAKE_* definitions are the ones that are used in the code, so drop the unused GPIO_*_WAKE_EN definitions for the same bits. Also move the GPIO_WAKE_* definitions to the place the GPIO_*_WAKE_EN ones were before this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I622673cc72107908b525a65212061062f32e13dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: use bit definitions for masksFelix Held
All bits covered by the bit masks GPIO_INT_ENABLE_MASK, GPIO_PULL_MASK, GPIO_STATUS_MASK and GPIO_WAKE_MASK already have definitions in the code so use those instead of magic numbers. TEST=Timeless build results in identical image for amd/mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: remove unneeded line breakFelix Held
The definitions of GPIO_INT_ENABLE_STATUS_DELIVERY and GPIO_TIMEBASE_62440uS fit into 96 characters, so remove the unneeded line breaks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b9c3885259b9acf0539eed14e23fbbb0deccea7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/common/block/include/gpio_defs: drop 8k pullup defineFelix Held
The corresponding bit is marked as reserved in the following versions of the documentation for all SoCs using this code: Mullins: BKDG #52740 Rev 3.05 Stoneyridge: BKDG #55072 Rev 3.04 Raven1, Picasso: PPR #55570 Rev 3.16 & 3.18 Raven2: PPR #55772 Rev 3.08 Cezanne: PPR #56569 Rev 3.03 The old Rev 3.14 of the Picasso PPR #55570 had the bit 19 defined as PullUpSel, but this is no longer the case in newer versions. It is unclear if this got de-featured or if it was never present in the silicon. To be consistent with the current documentation, drop this define. This patch also change the definition of GPIO_PULL_MASK to only cover the bits used for the feature. The Cezanne PPR #56569 Rev 3.03 states a default value of 0 for this bit after reset, so the resulting values in the register aren't expected change. The other PPRs/BKDGs don't specify a reset value for this bit, but it's likely safe to assume that all SoCs that use the new GPIO interface use the same GPIO building block. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/amd/common/block/include/acpi: fix reference to main acpi includeFelix Held
commit e0844636aca974449c7257e846ec816db683d0b9 (acpi: Move ACPI table support out of arch/x86 (2/5)) moved the main acpi header file from arch/x86/include/acpi/acpi.h to include/acpi/acpi.h, so change the comment in here to point to the current location. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5fddd1cd5eefd83816b1c966b5c7edf53eb2486d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/amd/common/block/include/gpio_defs: add GPIO IRQ status registersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I585691038690f1d6855ab09f1ca5791a18cfdbfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/59590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/amd/common/block/include/gpio_defs: use lower case in hex numbersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icb1c7b243f655225347ba2a78c80e6e8653e8cda Reviewed-on: https://review.coreboot.org/c/coreboot/+/59589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-16lib/prog_loaders, soc/amd/: Make payload_preload use cbfs_preloadRaul E Rangel
Now that CBFS has this functionality built in, we no longer need to manually code it. payload_preload used to use the payload_preload_cache region to store the raw payload contents. This region was placed outside the firmware reserved region, so it was available for use by the OS. This was possible because the payload isn't loaded again on S3 resume. cbfs_preload only uses the cbfs_cache region. This region must be reserved because it gets used on the S3 resume path. Unfortunately this means that cbfs_cache must be increased to hold the payload. Cezanne is the only platform currently using payload_preload, and the size of cbfs_cache has already been adjusted. In the future we could look into adding an option to cbfs_preload that would allow it to use a different memory pool for the cache allocation. BUG=b:179699789 TEST=Boot guybrush and verify preloading the payload was successful CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-15soc/amd/common/block: Add spi_hw mutexRaul E Rangel
There are currently two users of the SPI hardware, the LPC SPI DMA controller, and the boot_device_rw device. We need to ensure exclusivity to the SPI hardware otherwise the SPI DMA controller can be interrupted and it will silently skip transferring some blocks. Depending on the SPI speed, this change might add a small delay when clearing the elog since a DMA transaction might be in flight. I'll continue optimizing the boot flow to avoid the delay. BUG=b:179699789 TEST=Hack up the code to interleave SPI transactions and verify this patch fixes the silent data corruption. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5eee812a6979c8c0fb313dd2fbccc14b73d7d741 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-12soc/amd/common/block/lpc: Set FSP-S/M alignment to 64 when using SPI DMARaul E Rangel
This will enable reading FSP-S/M using the SPI DMA controller. BUG=B:179699789 TEST=Build guybrush with SPI DMA enabled and verify alignment is set Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09amd/sata: Remove the weak functionZheng Bao
BUG=b:140165023 Change-Id: I1908f727a7be1e33cbfd273b7261cbd989a414fe Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04soc/amd/common/block/spi: Add prompt to SOC_AMD_COMMON_BLOCK_SPI_DEBUGRaul E Rangel
Makes it so I can enable SPI debugging without modifying the source. BUG=b:179699789 TEST=Add CONFIG_SOC_AMD_COMMON_BLOCK_SPI_DEBUG=y to my .config Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie3815e0398b5268874039196a625fc29dd3dc3d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04soc/amd/common/block/lpc: Set CBFS_CACHE_ALIGN to 64 when using SPI DMARaul E Rangel
AMD platforms require the destination buffer to be 64 byte aligned when using the SPI DMA controller. BUG=b:179699789 TEST=gdb -ex 'p cbfs_cache' /tmp/coreboot/guybrush/cbfs/fallback/ramstage.debug $1 = {buf = 0x0, size = 0, alignment = 64, last_alloc = 0x0, second_to_last_alloc = 0x0, free_offset = 0} Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I228372ff19f958c8e9cf5e51dcc3d37d9f92abec Reviewed-on: https://review.coreboot.org/c/coreboot/+/58707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-04amd/i2c: Remove the weak functionZheng Bao
BUG=b:140165023 Change-Id: Ieedd6c9f3abeed9839892e5d07127862cd47d57f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-02include/device/pci_ids,soc/amd/common/block/lpc: drop duplicate PCI IDsFelix Held
PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS redefine the same values that are already defined by PCI_DEVICE_ID_AMD_CZ_LPC and PCI_DEVICE_ID_AMD_CZ_SMBUS, so drop PCI_DEVICE_ID_AMD_FAM17H_LPC and PCI_DEVICE_ID_AMD_FAM17H_SMBUS. Also add some comments to the places in the code where the defines are used to clarify which ID is used on which hardware generation. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0b3d7b5a886ccc76d82ada6be4145e85fd51ede Reviewed-on: https://review.coreboot.org/c/coreboot/+/58696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-02soc/amd/common/block/cpu: Add support for cbfs_cache regionRaul E Rangel
This change adds the cbfs_cache region into the x86 memlayout. The SoC or mainboard can decide how big the region should be by specifying CBFS_CACHE_SIZE. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache region wasn't added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-02psp_verstage: convert relative address in EFS2Kangheui Won
Addresses in AMD fw table with EFS gen2 are relative addresses, but PSP doesn't accept relative addresses in update_psp_bios_dir(). Check for EFS gen2 and convert them as needed. BUG=b:194263115 TEST=build and boot on guybrush and shuboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I95813beba7278480e6640599fcf7445923259361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-01amd/lpc: Remove the weak functionZheng Bao
BUG=b:140165023 Change-Id: Idb4613dc08c8dee6c92b4dabb39c2f5c189471aa Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-27soc/amd/common/block/graphics: add missing GPU PCI IDsFelix Held
Since the iGPU PCI device IDs for AMD Renoir (family 17h, model 60h) and Lucienne (family 17h, model 68h) are already defined in pci_ids.h, also add them to the pci_device_ids list in the common AMD graphics support block. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1c554d21eece182ecea7b09b45b7aa8a733425d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-25soc/amd/common/block/lpc/Makefile: simplify handling spi_dma.cFelix Held
Use the verstage_x86 class for the spi_dma.c target instead of using the verstage class and guarding it with !VBOOT_STARTS_BEFORE_BOOTBLOCK. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b8cafd1ef17df8c485f6594bc0928cea88e436b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps, mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of all 4 functions listed above against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21soc/amd/common/block/cpu/smm/finalize: simplify finalize_coresFelix Held
The local variable int r isn't needed, so remove it. This is a preparation to change the return type of mp_run_on_all_cpus from int to enum cb_err which will be done in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4c454cbfcc581be41ea3463ea6f852a72886128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-20soc/amd/common/block/cpu: Remove magic number in memlayoutRaul E Rangel
The SPI DMA controller can only perform transactions on a cache line boundary. This change removes the magic number and uses the #define to make it clear. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-19soc/amd/common/block/include/psp_efs: don't typedef structFelix Held
Don't use a typedef for the embedded_firmware struct so that it's clearer that this is a struct. TEST=Timeless build for google/guybrush results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97a02c350af57c8f58014aaf7dda8b4796905ff3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19soc/amd/common/block/include/psp_efs: rename embedded_firmware elementsFelix Held
The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia70e97f10f4fa0ac63cc65a33ecdc956538482b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-18ACPI: Have common acpi_fill_mcfg()Kyösti Mälkki
As long as there is only one PCI segment we do not need more complicated MCFG generation. Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-15soc/amd/common: move configure_espi_with_mb_hook implementationFelix Held
Move the actual implementation of configure_espi_with_mb_hook out of the header file and into the espi_util.c file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1106e69a52bf329a41e8e12fd09db846310b102a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd: make configure_espi_with_mb_hook call conditionalFelix Held
If a system doesn't use eSPI or has the eSPI interface already configured in verstage on PSP, not calling configure_espi_with_mb_hook from fch_pre_init makes it a bit more obvious that the eSPI interface initialization will be skipped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia77b83d56a5dab1bac6cfbbd92d33aa60a9e8b89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/common/include/espi: rename configure_espiFelix Held
Rename configure_espi to configure_espi_with_mb_hook to clarify that this function will call into the mb_set_up_early_espi function in the mainboard-specific code if it exists. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5d0f099288b0100242629c736dd69a8add977b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/common/block/i2c: implement proper read_resourceFelix Held
Before this patch the reservation of the MMIO region of the I2C controllers was done in the LPC controller PCI device despite the I2C controllers already being devices in the devicetree. This patch implements this functionality as read_resources function of the I2C device instead. This will only reserve the memory when the I2C devices are enabled in devicetree which is a change from the previous behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58307 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15soc/amd/common/block/lpc: simplify eSPI part of MakefileFelix Held
Since espi_util.c is also built in the case of verstage on PSP, we can just add it to all stages. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I65e07c356aac73c5de2d9ce5582434872a223c19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common/block/spi: Support fast speed overrideKarthikeyan Ramasubramanian
Add support to override SPI ROM fast speed based on board version. This will allow boards to start at lower speeds during bringup and then switch to higher speeds after assessing the signal integrity. Also implement a default no-op override. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common: Add support to read and set SPI speeds from verstageKarthikeyan Ramasubramanian
Currently all SPI speed configurations are done through EFS at build time. There is a need to apply SPI speed overrides at run-time - eg. based on board version after assessing the signal integrity. This override configuration can be carried out by PSP verstage and bootblock. Export the APIs to set and read SPI speeds from both PSP verstage and bootblock. BUG=None TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I281531e506b56173471b918c746f58d1ad97162c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common/block/espi_util: Refactor eSPI SetupKarthikeyan Ramasubramanian
eSPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also eSPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating eSPI very early in fch_pre_init if verified boot starts after bootblock and eSPI is enabled. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-12soc/amd/common/block/include/psp_efs: use unsigned type for bitfieldFelix Held
For 1 bit long bit fields an unsigned type should be used. In this case uint32_t is used instead of a generic unsigned int for both consistency reasons with the rest of the file and to clarify that the bits will be packed into a 32 bit memory location. TEST=Resulting image of a timeless build for google/guybrush results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic630d1709174d90336746bc37da504437c12643c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11soc/amd/common/include/lpc: add definitions for LPC LDRQ control bitsFelix Held
The definitions of bit 9 and 10 somehow got swapped between Picasso and Renoir/Cezanne, so put those in the Cezanne-specific header file. The reference code writes the same values to the raw bits in both, so we probably would still get away with putting this into the common header, but it's better to keep the defines consistent with the documentation in all cases. Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03 and cross-checked to be compatible with the Picasso PPR #55570 Rev 3.16. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-27soc/amd/common/block/include/acpimmio_map: add AOAC acronym in commentFelix Held
The Always On Always Connected block is referenced as AOAC in the code, so add that acronym in the comment and change the "Connect" to "Connected". Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6a23e0ccff62c6ceddae70e1bef5c5abf872c495 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24soc/amd/common: move block/pi out of the block folderFelix Held
Since the binaryPI glue code is specific to a binary interface, but not for a hardware block, move it out of the common blocks directory. This also brings the binaryPI support in line with the FSP support which is used on the newer generations. This also drops the SOC_AMD_COMMON_BLOCK_PI Kconfig option and makes use of the already existing SOC_AMD_PI Kconfig option instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I014e538f2772938031950475e456cc40dd05d74c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24soc/amd/common/block: move binaryPI S3 block into PI blockFelix Held
The code in soc/amd/common/block/s3 is specific to the AMD binaryPI coreboot integration, so move the code to soc/amd/common/block/pi. This drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking process, we don't lose support for any working configuration by only having one Kconfig option for both parts. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd/common/blocks/include: rename gpio_banks.h to gpio.hFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd/common/blocks: rename gpio_banks folder to gpioFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3dfcca2f126eb49c962b5cc32cbcf72e04f3f170 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd: rename program_gpios to gpio_configure_padsFelix Held
Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd,intel/common/include/gpio: improve documentation of overridesFelix Held
Explicitly point out that gpio_configure_pads_with_override will ignore GPIOs that are only in the override configuration, but not in the base configuration. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1bdfcac89b81fef773938133a2699897c6ee9415 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-22soc/amd/common/block/gpio_banks: Rework GPIO pad configurationFelix Held
Before this patch, gpio_configure_pads_with_override called program_gpios once for each GPIO that needed to be configured which resulted in base_num_pads - 1 unneeded master_switch_set/ master_switch_clr sequences for the gpio_configure_pads_with_override call. Instead implement gpio_configure_pads_with_override as the more generic function and program_gpios as a special case of that which passes an empty override configuration and override pad number to gpio_configure_pads_with_override. TEST=GPIO configuration and multiplexer register values are the same for all GPIOs on google/guybrush right before jumping to the payload before and after the patch. Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-21soc/amd/common/block/gpio_banks: add missing types.h includeFelix Held
In this file bool, uint8_t and uint32_t are used, so include types.h directly to have those types defined instead of relying to have those included indirectly via amdblocks/gpio_banks.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6f4626a50219fab818e8bc5087961a731b44e71b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17soc/amd/common/block/pi/image: replace stdbool.h include with types.hFelix Held
Apart from the bool type, uint8_t, uint32_t and uint64_t are used in this file, so include types.h instead of stdbool.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I30088d68132058f40b974fbaa822f322b58ed6c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-16soc/amd/common/block/pi: Add missing include stdbool.hRaul E Rangel
BUG=b:179699789 TEST=build morphius Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I298ce1ee436a5c8eb8375dc5fe55665bbf977463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-16drivers/intel/fsp2_0: Pass orientation to fsp_report_framebuffer_infoTim Wawrzynczak
Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets implementing the callback to pass in an orientation. BUG=b:194967458 BRANCH=dedede Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13soc/amd/common/block/cpu: Add missing includeRaul E Rangel
We use cpuid_eax to get the cpuid family. BUG=b:179699789 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib73e66241bb0cfd99a035c217c527338aa2d0e4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-09soc/amd/common/block/acpi/gpio: add warning for remote GPIO usageFelix Held
Right now the ACPI code doesn't support accessing the remote GPIO block yet, so don't generate invalid remote GPIO access functions and warn about those being unsupported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id364a59c9650bf4e3633b494b01ab23c0bbc50b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-09-09soc/amd/common/block/gpio_banks: add remote GPIO supportFelix Held
Some AMD SoCs have a 5th GPIO bank, the remote GPIO bank, which isn't located right after the 4th GPIO bank, but instead at a different location inside the APCIMMIO region. A difference to the first 4 GPIO banks is that the corresponding GPIO MUX registers aren't in a separate bank, but at the end of the remote GPIO region. So this remote GPIO region only supports 48 GPIOs with a 32 bit configuration register each and has the 8 bit GPIO MUX registers beginning at offset 0xc0 in the remote GPIO region. For now using the remote GPIOs from verstage on PSP isn't supported. To support this, it would need to map acpimmio_remote_gpio and update the pointer like it already does for acpimmio_gpio0, acpimmio_iomux and a few others. BUG=b:194524995 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic8d7ff677a99381a5558782b80b0c4cae67602db Reviewed-on: https://review.coreboot.org/c/coreboot/+/56810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09soc/amd/common/block/acpimmio: add remote GPIO bank ACPIMMIO regionFelix Held
Currently coreboot for the AMD SOCs only supports accessing the up to 4 main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne have another GPIO bank in the ACPIMMIO region that can contain up to 48 GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The first 48 DWORDs of that ACPIMMIO bank are the 32 bit wide GPIO registers and beginning at offset 0xc0 it has the corresponding 8 bit wide GPIO MUX registers. BUG=b:194524995 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-09soc/amd/common/block/include/i2c: introduce I2C_RESET_SCL_PIN macroFelix Held
Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins array that is used for the sb_reset_i2c_peripherals call to bring the I2C buses into a defined state. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-08cpu/x86/tsc: Deduplicate Makefile logicAngel Pons
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc` is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig option is enabled. Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and drop the now-redundant inclusions from platform code. Also, deduplicate the `UDELAY_TSC` guards. Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08soc/amd/common/block/gpio_banks: add comment about acpimmio_* symbolsFelix Held
Suggested-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0016a6c7d6581cb261cab6178268c1a86b89c839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56831 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08soc/amd/common/block/gpio_banks: inline iomux_read8 and iomux_write8Felix Held
Since both functions are only called from one function each, inline them into those functions. Also get_gpio_mux just returned the return value of iomux_read8, so there were two functions with identical functionality which shouldn't be the case. Suggested-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5662d0226edb25a9954fa47b42e208729a79e5a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56830 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08soc/amd/common/block/gpio_banks: factor out gpio_mux_ptrFelix Held
This aligns the GPIO MUX access more with the GPIO control register access and will facilitate adding support for the remote GPIO bank. Also change the GPIO number argument type to gpio_t. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4054656c5cc23ea942e8dd370fbbffca304755d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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