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Since mst_t is a union of the struct containing the lower and higher 32
bits and the raw 64 bit value, the address of the microcode update can
be directly written to the raw value instead of needing to split it into
the lower and higher 32 bits and assigning those separately.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I51c84164e81477040a4b7810552d3d65c0e3656b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Since mst_t is a union of the struct containing the lower and higher 32
bits and the raw 64 bit value, the address of the bootblock_resume_entry
can be directly written to the raw value instead of needing to split it
into the lower and higher 32 bits and assigning those separately.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7ebab1784ec592e18c29001b1cf3ee7790615bf8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This separates the SPL fusing function into a separate C file which can
be excluded if it is not needed. This allows the psp_set_spl_fuse()
function to be made static again as the state of the function will
always match the boot_state entry.
Move the required #defines to the common header file so they can be
used by both psp_gen2.c & spl_fuse.c.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ifbc774a370dd35a5c1e82f271816e8a036745ad5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73655
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Even though right now TSEG will always be located below 4GB, better not
make assumptions in the SMM relocation code. Instead of clearing the
higher 32 bits and just assigning the TSEG base and per-core SMM base to
the lower 32 bits of the MSR, assign those two base addresses to the raw
64 bit MSR value to not truncate the base addresses. Since TSEG will
realistically never be larger than 4GB and it needs to be aligned to its
power-of-two size, the TSEG mask still only needs to affect the lower
half of the corresponding MSR value.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1004b5e05a7dba83b76b93b3e7152aef7db58f4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Since mst_t is a union of the struct containing the lower and higher 32
bits and the raw 64 bit value, there's no need to convert the lower and
higher 32 bits into a 64 bit value and we can just use the 64 bit raw
value.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5923df84f0eb3a28ba6eda4a06c7421f4459e560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The get_threads_per_core function isn't specific to the non-CAR CPUs and
also applies for Stoneyridge and even for family 16h model 30h outside
of soc/amd, so move it from the non-CAR-specific cpu.c file to the
common AMD SoC cpu.c file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I05946f163112ff93f33139f6c43fed5820fd0a3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Picasso already uses the Cxxx ACPI CPU device naming scheme, due to it
being what the AGESA reference code uses. We initially relied on the
AGESA/FSP generated SSDT for the P- and C-state support before we had a
native implementation for this in coreboot. The Cxxx naming scheme can
also be used for the other AMD SoCs except Stoneyridge which is pre-Zen
and doesn't select SOC_AMD_COMMON_BLOCK_NONCAR. The main advantage of
using Cxxx instead of CPxx is that the Cxxx scheme supports systems with
more than 256 CPU threads.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I884f5c0f234b5a3942dacd60847b2f095f9c0704
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73620
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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AMD SoCs currently only log the GPE# when an XHCI controller wakes the
system. Add code to log XHCI wake events to the elog.
BRANCH=guybrush
BUG=b:186792595
TEST=builds
Change-Id: Ic0489e1df55c4e63cb8a306099e3f31c82eebd58
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This adds checks for three more error bits before requesting that the
SPL fuses are updated.
- While I'm here, I'm adding the include of types.h which was previously
done through other include files, but should be done independently.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I87a7d40850c4e9ddbb2d1913c1588a919fdb29d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Use the presence of an SPL (Software Patch Level) file to trigger the
function that reads and writes the SPL fuses. The current Kconfig
option will be used to decide to write the fuses. This allows us to
see the state of the SPL update bit which determines whether or not
SPL fusing is allowed and needed before enabling the fusing.
- Refactor a bit to prepare for following changes.
- Update phrasing
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7bd2798b984673a4bd3c72f3cab52f1c9a786c67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Now that the code using the ACPI_SSDT_PSD_INDEPENDENT Kconfig symbol is
moved to soc/amd/common/block/acpi/cpu_power_state.c, also move the
Kconfig symbol to the Kconfig file in this directory.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ide18111df38d4e9c81f7d183f49107f382385d85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Introduce the get_cstate_io_base helper function that write_cstate_entry
can call directly to get the C state control IO base address instead of
having get_cstate_info pass this Io address to each write_cstate_entry
call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I4cc80ded0a2fbc2dee9ca819e86284d9ffd58685
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The bit position of the P state enable bit in the 8 P state MSRs is
identical for all AMD chips including the family 16h model 30h APU that
lives outside of soc/amd. The other bits in those 8 MSRs are more or
less family- and model-specific.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia69c33e28e2a91ff9a9bfe95859c1fd454921b77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The implementations of get_pstate_info of Picasso, Cezanne, Mendocino,
Phoenix and Glinda are identical, so factor it out and move it to the
common AMD SoC code. The SoC-specific get_pstate_core_freq and
get_pstate_core_power functions remain in the SoC-specific code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe0494f1747f381a75b3dd71a8cc38fdc6dce042
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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With the exception of the generate_cppc_entries call, the
implementations of generate_cpu_entries of Picasso, Cezanne, Mendocino,
Phoenix and Glinda are identical, so factor it out and move it to the
common AMD SoC code. Since all SoCs that support CPPC already select the
SOC_AMD_COMMON_BLOCK_ACPI_CPPC Kconfig option, this can be used to only
call generate_cppc_entries for platforms where it is available.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71323d9d071b6f9d82852479b60dc56c24f2b9ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Instead of using a magic constant in the bit_offset field of the C state
resource for the C1 state that's entered via the MWAIT instruction, use
the existing ACPI_FFIXEDHW_CLASS_MWAIT define. This value is checked by
acpi_processor_ffh_cstate_probe in the Linux kernel.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9edc681efab15b5ceba91c8105f7dc6d687d8be8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Introduce the get_cstate_info helper function that populates the caller-
provided cstate_values array with the data returned by the SoC-specific
get_cstate_config_data function. From the array get_cstate_config_data
returns, only the ctype, latency and power fields are used, so the rest
can be left uninitialized. Those 3 fields are compile-time constants.
For each entry, write_cstate_entry will generate the corresponding
resource information from the given data. In the C1 case where ctype is
1, the state is entered via a MWAIT instruction, while the higher C
states are entered by doing an IO read from a specific IO address. This
IO address is x - 1 bytes into the IO region starting at
MSR_CSTATE_ADDRESS for the Cx state. So for example C2 is entered by
reading from the C state IO base address + 1. This resource information
is generated during runtime, since the contents of MSR_CSTATE_ADDRESS
aren't necessarily known at compile-time.
MAX_CSTATE_COUNT is introduced so that the caller can allocate and pass
a buffer with space for the maximum number of C state entries. This
maximum number corresponds to the number of IO addresses the CPU traps
beginning from MSR_CSTATE_ADDRESS. In practice, it's unlikely that more
than 3 or maybe 4 C states will be available though.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2c36c1d604ced349c609882b9d9fe84d5f726a8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The legacy ACPI CPU control registers in IO space where the first 4 IO
locations control the CPU throttling value don't exist any more on the
Zen-based CPUs. Instead this IO address is written to MSR_CSTATE_ADDRESS
in set_cstate_io_addr which will cause accesses from the 8 IO addresses
beginning with ACPI_CSTATE_CONTROL to be trapped in the CPU core. Reads
from those IO addresses will cause the CPU to enter low C states.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2c34e201cc0add1026edd7a97c70aa57f057782b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Add a new parameter STT_ALPHA_APU' for each DPTC mode.
BUG=b:257149501
BRANCH=None
TEST=Check if the STT value matches the expected setting.
Change-Id: Ib27572712d57585f66030d9e927896a8249e97a7
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
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Instead of adding the P-state number to the PSTATE_0_MSR number to get
the P-state MSR number for the rdmsr call, provide a macro that directly
calculates the MSR number for a given power state. Also drop the unused
PSTATE_[1..4]_MSR definitions which also didn't cover all P-state MSRs
available in the hardware.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If85acf556efe82c209e1608e56c05f7a2a748403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use enum cb_err to return an error/success state instead of an int in
get_nv_rdev and get_nv_rdev_rw.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I73706a93bc1dbc8556e11885faf7f486c468bea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73317
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The bool type is used although stdbool.h isn't included. Include types.h
which will include both stdint.h and stdbool.h
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5213ddae3ceb36e0b2e09f8ef3f7f414ebdf187f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73316
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If a mainboard has RECOVERY_MRC_CACHE and the recovery mode is enabled,
then use APOB data from that section and make any updates to that
section. Otherwise continue to use DEFAULT_MRC_CACHE section.
BUG=b:270569389
TEST=Build and boot to OS in Skyrim.
When in normal mode, DEFAULT_MRC_CACHE is used.
Normal Mode Boot1:
------------------
[DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes)
[INFO ] APOB RAM hash differs from flash
[SPEW ] Copy APOB from RAM 0x02001000/0x1db18 to flash 0x0/0x1e000
[DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes)
[DEBUG] SF: Successfully erased 122880 bytes @ 0x0
[INFO ] Updated APOB in flash
Normal Mode Boot2:
-----------------
[DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes)
[DEBUG] APOB hash matches flash
When the device is in recovery mode, RECOVERY_MRC_CACHE is used.
Recovery Mode Boot1:
--------------------
[DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes)
[INFO ] APOB RAM hash differs from flash
[SPEW ] Copy APOB from RAM 0x02001000/0x1db18 to flash 0x650000/0x1e000
[DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes)
[DEBUG] SF: Successfully erased 122880 bytes @ 0x650000
[INFO ] Updated APOB in flash
Recovery Mode Boot2:
--------------------
[DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes)
[DEBUG] APOB hash matches flash
Switch from Recovery Mode to Normal Mode:
-----------------------------------------
[DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes)
[DEBUG] APOB hash matches flash
Switch from Normal Mode to Recovery Mode:
-----------------------------------------
[DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes)
[DEBUG] APOB hash matches flash
Change-Id: I93f357e407c98b6e5fca495f4f779fad54a3430f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Add option for mainboards to target builds for SimNow.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id765437b69f1bc3a9f9d7858edcd27e687d5a7f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Rather than explicitly checking for Recovery or Developer mode via
vboot, use display_init_required() so that vboot is not required, and
other instances where the display is needed pre-OS (such as when
applying a critical system update) are covered as well.
With this change, SoCs implementing selective GOP init will need to
select VBOOT_MUST_REQUEST_DISPLAY in order for display_init_required()
to not assert on compilation.
BUG=b:255812886
TEST=build/boot skyrim
Change-Id: Iac7e06863764a9f21c8a50fc19050cb5a6627df2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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The EFS entry at offset 0x14 can point to either the first level PSP
directory table or to the PSP combo directory structure that was used
before the introduction of the AMD A/B recovery scheme. This scheme is
not to be confused with the VBOOT scheme. The PSP verstage code checks
if the header this entry points to begins with the PSP_COOKIE, which
indicates the entry is a first level PSP directory table. Due to that,
the EFS entry at offset 0x14 is always expected to point to a PSP
directory table, so rename combo_psp_directory to new_psp_directory to
match the actual usage. This EFS entry that points to the PSP directory
table is called new_psp_directory, since the entry at EFS offset 0x10
was used on some early AMD chips to point to the older PSP directory
table and that one is already called psp_directory. amdfwtool uses the
same naming scheme for those two PSP directory table pointers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I10f19ee63f8d422433dba64402d84fd6bb9e0f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73083
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Write the SHA256 hash of the cached VBIOS data when saving to FMAP,
and use it to validate the data read from FMAP on subsequent boots.
Add TPM2 as a dependency to the selection of VBIOS_CACHE_IN_FMAP.
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: I9c8f23b000b90a1072aeb7a57d3b7b2b2bc626dc
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72402
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of using PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC), use the equivalent
SMBUS_DEVFN define.
Even though the FCH IOAPIC is in the LPC part of the FCH, it needs the
IVRS IOAPIC table's source_dev_id field set to SMBUS_DEVFN which is the
function 0 of the FCH PCI device. LPC is function 3 of the FCH device.
When assigning LPC_DEVFN to source_dev_id, the kernel from Ubuntu
2022.04 LTS complains about the IOAPIC part of the IVRS table being
wrong:
AMD-Vi: [Firmware Bug]: : No southbridge IOAPIC found
AMD-Vi: Disabling interrupt remapping
With SMBUS_DEVFN being used as source_dev_id, no such error is reported.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I8470d67b2513031e75fb422d4c1c181e017ace0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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One of the main functions performed by the FSP GOP driver is to modify
the ATOMBIOS tables (part of the VBIOS) in memory based on the display
output configuration. This device-specific modified VBIOS can be cached
in a FMAP region specific for that purpose, then loaded into memory
instead of the "generic" VBIOS, saving the ~130ms execution time of the
GOP driver.
As this approach only works when no pre-OS display output is needed,
limit its use to ChromeOS builds, with the GOP driver enabled, and
not booting in either recovery or developer modes.
SoCs supporting this feature will need to selectively run the FSP GOP
driver as needed, using the same criteria used here to determine
whether to load the VBIOS from CBFS or from the FMAP cache.
Boards utilizing this feature will need to add a dedicated FMAP region
with the appropriate name/size, and select the required Kconfig options.
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: Ib9cfd192500d411655a3c8fa436098897428109e
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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The AMD SimNow tool supports fast logging through an IO port. Add a new
console to support SimNow logging through port 80.
TEST=observe significant speed improvements on SimNow console log
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I42a431f48ea14ba4adacbd4a32e15abe7c5e4951
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Since all SoCs define the df_mmio_control union for the bits used in the
code, data_fabric_print_mmio_conf can take advantage of that and also
print a decoded version of those bits.
Output on Mandolin before the patch:
=== Data Fabric MMIO configuration registers ===
idx control base limit
0 93 fc000000 febfffff
1 93 10000000000 ffffffffffff
2 93 d0000000 f7ffffff
3 1093 fed00000 fedfffff
4 90 0 ffff
5 90 0 ffff
6 90 0 ffff
7 90 0 ffff
Output on Mandolin with the patch:
=== Data Fabric MMIO configuration registers ===
idx base limit control R W NP F-ID
0 fc000000 febfffff 93 x x 9
1 10000000000 ffffffffffff 93 x x 9
2 d0000000 f7ffffff 93 x x 9
3 fed00000 fedfffff 1093 x x x 9
4 0 ffff 90 9
5 0 ffff 90 9
6 0 ffff 90 9
7 0 ffff 90 9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06e1d3a3e9abd664f59f2bb852394e7f723f2b30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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To be able to handle a special case, add a per-SoC define for
DF_MMIO_REG_SET_SIZE instead of having this hard-coded as 4 in the
DF_MMIO_* macros. To avoid some duplication, also introduce the
DF_MMIO_REG_OFFSET macro.
TEST=Output from data_fabric_print_mmio_conf doesn't change on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67420a2973c8ef9a7f0ce19ddc0013de69731689
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Since the MMIO decode range registers in the data fabric are part of the
data fabric and not of the northbridge, replace the NB prefix with a DF
prefix to make this a bit clearer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ife5e4581752825e9224b50252955d485a067af74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This should make it a bit clearer that those registers are in the data
fabric configuration registers. Also move those defines right after the
register definition those are related to.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic107bd217f4af0a9ddfbe41aafd3c882aa968e22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Instead of just printing the register contents, normalize the contents
of the base and limit registers to actual MMIO addresses and then print
those. This will hopefully avoid some confusion caused by the shifted
addresses.
Output on Mandolin before the patch:
=== Data Fabric MMIO configuration registers ===
Addresses are shifted to the right by 16 bits.
idx control base limit
0 93 fc00 febf
1 93 1000000 ffffffff
2 93 d000 f7ff
3 1093 fed0 fedf
4 90 0 0
5 90 0 0
6 90 0 0
7 90 0 0
Output on Mandolin after the patch:
=== Data Fabric MMIO configuration registers ===
idx control base limit
0 93 fc000000 febfffff
1 93 10000000000 ffffffffffff
2 93 d0000000 f7ffffff
3 1093 fed00000 fedfffff
4 90 0 ffff
5 90 0 ffff
6 90 0 ffff
7 90 0 ffff
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda.
PCO supports the warm reset, and future chips can support it by setting
the SOC_AMD_SUPPORTS_WARM_RESET option.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72658
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>.
Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This register isn't used in coreboot and isn't defined in the Picasso
PPR #55570 Rev 3.18.
To enter a lower C-state, a read request to a special IO port is done.
The base address of this group of IO ports is configured in
set_cstate_io_addr via the MSR_CSTATE_ADDRESS and that read won't leave
the CPU. IIRC trying to put the MMIO mapping for entering the lower
C-states into the _CST package didn't work as expected when it was tried
on I think Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib189993879feaa0a22f6810c4bd5c1a0bc8c5a27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Since commit d5ab24cd4800 ("soc/amd/common/acpi/cppc: add nominal and
minimum frequencies") the fields that got added in CPPC version 3 get
populated, so remove the now outdated comment about the fields added in
version 3 always being set to CPPC_UNSUPPORTED.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4c975b42fc4f67329170801b871d6bbdf9637d04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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<gpio.h> chain-include <soc/gpio.h>.
Change-Id: I112e41ad4c7ee638954dfe3f1ddfeb10c138459a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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The device operations for the CPU bus are identical for all AMD SoCs, so
introduce a common device operations struct for this and use it in all
AMD SoC's chipset devicetrees as ops for the CPU cluster.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id32f89b8a33db8dbb747b917eeac3009fbae6631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Add an SVC call to get the state of Hardware Security Processor (HSP) in
AMD SoCs. This SVC call will be used from PSP verstage to get and
report HSP state.
BUG=b:198711349
TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state
is read and reported in the firmware logs.
Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The smu_sx_entry function is identical for all AMD SoCs, so introduce it
as common code that can be selected to be included in the build via the
SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY Kconfig option. The only SoC-specific
difference in this function is the ID of the SMC_MSG_S3ENTRY message
which is defined in each SoC's soc/smu.h include file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I49758e9333a351d8e50e8f1b53a7f00fbe89866c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71875
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Change-Id: Id24a7c7db24f49672df9d5ceefec5b7596f23e09
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Replace spaces with tabs for consistency.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I65b9bec7443094dfd2f6b0d6b11e0100023873b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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There's no need to call die() in the case that the MMIO address of the
I2C controller is NULL, so handle this case by returning a failure
instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12c143916ad551c56cc4ff75ae23754018817505
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Since soc_get_common_config will either return a valid pointer or cause
a linking error, this function will also return a valid pointer or cause
a linking error, so no need for additional runtime checks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99661247b9f8f47a708e3a6ff3f9e5359b505509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70739
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Improve the espi_set_initial_config implementation so that a failure in
there due to an invalid configuration won't call die() and stop booting
at this point, but return an error to the caller so that the rest of the
eSPI configuration will be skipped.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97f730778a190c4485c4ffe93edf19bcbaa45392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Improve the eSPI pin configuration setup so that a failure in there
won't call die() and stop booting at this point, but return an error to
the caller so that the rest of the eSPI configuration will be skipped.
This will prevent an early boot failure if the EC is missing or the eSPI
interface is in a non-functional state. Also slightly shorten the
function names so that the code still fits into 96 chars.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice2d3a791d6a464eff4fb69d02aeca0bfe580be2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70730
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
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<device/mmio.h>` chain-include `<arch/mmio.h>:
https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes
Also sort includes while on it.
Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Include <amdblocks/gpio_defs.h> instead of "gpio_defs.h", since
gpio_defs.h is not only visible in a local scope, but also as
<amdblocks/gpio_defs.h>.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab3e5bb235a5b1bc995b6cf8710f0d8c1886142d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70432
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=IVRS table doesn't change on amd/mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5be04bc91425480992fcad12f8720738f9ca490e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70357
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fixing documentation of PAD_INT macro and replacing spaces with a tab to
match the rest of the documentation.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I72a2578ce21dd10b3beb65c706440c3379f216d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70281
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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For the most part, this doesn't change any post codes, simply making the
existing post-codes into macros.
picasso/romstage.c did get a couple of post codes removed to match the
other files.
The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global
at some point, while the POST_AGESA and POST_PSP codes would stay AMD
specific.
Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update acpigen_write_alib_dptc() to support extra 5 thermal profiles.
User can use these profiles for dynamic thermal table switching support.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68470
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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Calling setup_ioapic() was only correct for the
IOAPIC routing GSI 0..15 that mimic legacy PIC IRQs.
Change-Id: Ifdacc61b72f461ec6bea334fa06651c09a9695d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Tested on google/vilboz (running the PCI rom with yabel).
Change-Id: Icd72c4eef7805aacba6378632cbac7de9527673b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Now that we have a common init_tables in all mainboards using AMD SoCs,
both the population of the fch_pic_routing and fch_apic_routing arrays
and the definition of those arrays can be moved to the common AMD SoC
code to not have the code duplicated in all mainboards.
BUG=b:182782749
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Explicitly cast integers to fix building for long mode.
Change-Id: I9f56e183563c943d1c2bd0478c41a80512b47c5e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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On certain mainboards due to hardware design limitations, certain SPI
Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to
override SPI read modes in boards which do not have hardware
limitations. Currently there is an API to override SPI fast speeds.
Update this API for mainboards to override SPI read mode as well.
BUG=b:225213679
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~25 ms with 100 MHz SPI speeds.
Before:
11:start of bootblock 688,046
14:finished loading romstage 30,865
16:FSP-M finished LZMA decompress (ignore for x86) 91,049
Total Time: 1,972,625
After:
11:start of bootblock 667,642
14:finished loading romstage 29,798
16:FSP-M finished LZMA decompress (ignore for x86) 87,743
Total Time: 1,943,924
Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other
SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times
slightly.
Time PCO Others
1mS 0.915mS 1.220mS
2mS 2.013mS 2.684mS
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69209
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the generic data_fabric_acpi_name function and device ops to common
code.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I12053389a12081ddd81912a647bb532b31062093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Morgana/Glinda have a different register mapping for data fabric access,
although the registers themselves are mostly compatible. The register
layouts defined by each soc capture the differences and the common code
can use those.
Move the register offsets to soc headers and update the offsets for
morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254,
rev 1.51
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Now that the socs have defined the DF FICAA and MMIO Control registers,
update the common code to use them.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia5566f7af6cf5444fc8c627e004dd08185468c77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The data_fabric_set_mmio_np function is effectively identical, so move
it to common code.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Also sort includes.
Change-Id: Iea29938623fe1b2bcdd7f869b0accbc1f8758e7a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I547671d2bcfe011566466665b14e151b8ec05430
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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Adding coreboot's postcodes to the smart trace buffer lets us see the
entire boot flow in one place.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This allows platforms that support AMD's STB (Smart Trace Buffer) to
print the buffer at various points in the boot process.
The STB is roughly a hardware assisted postcode that captures the
time stamp of when the postcode was added to the buffer. Reading
from the STB clears the data.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8d78c0e86b244f3bd16248edf3850447fb0a9e2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Factor out the `gpp_dxio_update_clk_req_config` function as it will be
useful for other AMD SoCs.
BUG=b:250009974
TEST=Ran on nipperkin device, verified clk req settings match enabled
devices
Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Instead of using magic constants for the fch_pic_routing and
fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the
common code headers and use this definition. This also allows to drop
the static assert for the array sizes. In the Stoneyridge mainboard code
the equivalent arrays are named mainboard_picr_data and
mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array
size there.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Define the fch_irq_routing struct once in a common header file instead
of in every mainboard's code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68817
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To enable RO CBFS verification in AMD platforms with PSP verstage,
metadata hash for RO CBFS is kept as part of verstage. This means any
updates to RO CBFS, before WP is enabled, requires updating the
metadata hash in the verstage. Hence keep the metadata hash outside the
signed range of PSP verstage. This means the metadata hash gets loaded
as part of loading PSP verstage while still being excluded from the
verification of PSP verstage.
This change keeps the metadata hash outside the PSP footer data. This
will help to keep it outside the signed range of PSP verstage & aligned
to 64 bytes.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled with
both x86 and PSP verstage.
Change-Id: I308223be8fbca1c0bec8c2e1c86ed65d9f91b966
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68135
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that the SoC-specific UART controller data and the common code part
are cleanly separated, move the code to the common AMD UART support
block folder. The code is identical to the UART code in Cezanne,
Mendocino, Morgana and Picasso while Stoneyridge doesn't use the parts
related to the MMIO device driver.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9429dac44bc02147a839db89d06e8eded7f1af2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I97860292fd3cd0330fec40edb31089cd6608906b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3deae150cd1e20fff6507a0f0ba6a375fca430e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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The SoC's uart_info structs all use the same anonymous uart_info struct
definition, so create a named struct for this in the common AMD SoC UART
header and use it in the SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id183a3c838c6ad26e264c2a29f3c20b00f10d9be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59985f283f1694beeacb0999340111146fa3f39b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This code is identical for all non-CAR AMD SoCs, so factor it out to
soc/amd/common/block/cpu/noncar/bootblock.c to avoid code duplication.
Also integrate the bootblock.c improvement to include cpu/cpu.h which
provides cpuid_eax from commit 68eb439d8091 ("soc/amd/picasso: Clean up
includes").
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I42e4aa85efd6312a3ab37f0323a35f6dd7acd8e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Rename soc/amd/common/block/cpu/smm/smi_ampc_helper.c to smi_apmc.c and
add the fch_apmc_smi_handler function.
Remove the duplicated function from picasso, cezanne, mendocino, and
morgana SoC.
The stoneyridge soc does not implement the APM_CNT_SMMINFO handler, so
give the handler a unique name that does not conflict with the common
handler name.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2e6fb59a1ee15b075ee3bbb5f95debe884b66789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68441
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Cezanne has two SATA controllers, but doesn't select
SOC_AMD_COMMON_BLOCK_SATA, so it's not added to the SATA devices in the
Cezanne chipset devicetree.
Change-Id: If7f0a9638151cf981d891464a2c3a0ec5fc9c780
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This removed the need to maintain a PCI driver.
Change-Id: I43def81d615749008fcc9de8734fa2aca752aa9d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This removes the need for a PCI driver.
Change-Id: I6674d13f434cfa27fa6514623ba305af6681f70d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This removes the need for a PCI driver.
Change-Id: Iab75f8c28a247f1370f4425e19cc215678bfa3e5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If5447f9272183f83bc422520ada93d3cfd96551e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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This removes the need for a PCI driver.
Change-Id: I4b499013a80f5c1bd6ac265a5ae8e635598d9e6c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This removes the need for a PCI driver.
Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This removes the need for a PCI driver.
Change-Id: Id25016703d1716930d9b6c6d1dab5481b10aca17
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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This is not critical functionality and doesn't need a build-time error.
Having it as a build time error causes a chicken & egg issue where
the chipset needs to be added before it can be added to this file, but
the header file fails the build because the chipset is unknown.
It's not practical to exclude these files from the new platform builds
because the PSP functionality is thoroughly embedded into the coreboot
structure.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ib02bbe1f9ffb343e1ff7c2bfdc45e7edffe7aaed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Also add missing device/mmio.h include.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0f3f7ea36896c8e55c62acd93fe8fc4fb7c74b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67982
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Also include arch/mmio via device/mmio.h and not directly to have the
[read,write][8,16,32]p helper functions available.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id8573217d3db5c9d9b042bf1a015366713d508c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67981
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Also include arch/mmio via device/mmio.h and not directly to have the
[read,write][8,16,32]p helper functions available.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I51c6f5c73b41546b304f16994d517ed15dbb555f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67980
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Use just one function to get the chipset powerstate and add an argument
to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the
failure log accordingly.
TEST: compile tested and qemu emulation successfully run
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update acpigen_write_alib_dptc() to support "low/no battery mode",
which throttles the SOC when there is no battery connected or the
battery charge is critically low.
This is in preparation for enabling this functionality for Mendocino.
BUG=b:217911928
TEST=Build zork
TEST=Boot nipperkin
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Icea10a3876a29744ad8485be1557e184bcbfa397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66804
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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AMD CPUs have a convenient MSR that allows to set the SMBASE in the save
state without ever entering SMM (e.g. at the default 0x30000 address).
This has been a feature in all AMD CPUs since at least AMD K8. This
allows to do relocation in parallel in ramstage and without setting up a
relocation handler, which likely results in a speedup. The more cores
the higher the speedup as relocation was happening sequentially. On a 4
core AMD picasso system this results in 33ms boot speedup.
TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM
is correctly relocated with the BSP correctly entering the smihandler.
Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Locking SMM as part of the AP init avoids the need for
CONFIG_PARALLEL_MP_AP_WORK to lock it down.
Change-Id: Ibcdfc0f9ae211644cf0911790b0b0c5d1b0b7dc9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64871
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64870
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is the same for all supported AMD hardware.
Change-Id: Ic6b954308dbb4c5a2050f1eb8f15acb41d0b81bd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67617
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Since mono_time is now 64-bit, the utility functions interfacing with
mono_time should also be 64-bit so precision isn't lost.
Fixed build errors related to printing the now int64_t result of
stopwatch_duration_[m|u]secs in various places.
BUG=b:237082996
BRANCH=All
TEST=Boot dewatt
Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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