coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-01-14	soc/amd/piasso/uart: move get_uart_base prototype to common code header	Felix Held
	This will result in less code duplication when the common AMD SoC UART support gets used for more AMD SoCs. Change-Id: Id1786f32324de3e3947d792c599e2019705c5a85 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49373 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14	soc/amd/picasso: remove broken and unused legacy UART support	Felix Held
	The UARTs in the Picasso SoC are memory mapped, but there is also some hardware support that isn't used by any board to make the UARTs behave like the ones found on legacy x86 machines from the 90s. In the MMIO mode the MMIO address of the UART controller is passed to the OS via ACPI. The OS expects the base clock of the UART controller to be 48MHz (see the cz_uart_desc struct in drivers/acpi/acpi_apd.c and drivers/tty/serial/8250/8250_dw.c in the Linux kernel) in this case. It is also possible to enable additional decodes from four 8 byte legacy I/O locations used for serial ports to the different UART controllers, which doesn't disable the MMIO access though. The legacy I/O-mapped serial ports are usually expected to have a base clock of 16*115200Hz which the hardware can also provide to the UART's baud rate generator. So there are two possible valid configurations to use the UARTs; either MMIO access in combination with a 48MHz base clock or the legacy I/O decode with a ~1.8MHz base clock. The existing code unconditionally generates ACPI objects for all enabled UARTs, so those shouldn't be put into legacy mode and switching the base clock to ~1.8MHz was only done in the case that the UART was used as coreboot console UART which still used the MMIO access, but the lower base clock. Since no board even selects this option and it's rather invasive to properly implement this feature, just drop the corresponding broken code. TEST=SoC UART console still works on Mandolin. Change-Id: I26fa8fdfc781b583ba56ac4dbcbbfb6100e84852 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49371 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11	soc/amd/picasso: move UART console code to common folder	Felix Held
	Change-Id: Ibc9a4c05bdfc7cd3cd0eada67563386c95d2b50e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>