coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-12-20	amd/common/psp: Add BootDone command	Marshall Dawson
	After the PSP receives the MboxBiosCmdBootDone, it will no longer honor any command where the command-response buffer exists outside of SMM memory. Add the command and automatically execute it before booting the payload. BUG=b:69971683 TEST=Boot Kahlee and observe console log Change-Id: I8258a9e2f2627bf24342f927a3e7f49b49dc1d88 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20	amd/common/psp: Convert structure init to C99	Marshall Dawson
	Use C99 designated initializers for the psp_notify_dram() buffer structure. Change-Id: I2e18b3a2c19b8fb17d0f654b16def52517538957 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20	amd/common/psp: Assume PSP command register already set up	Marshall Dawson
	Remove the frequent setting/restoring of the PSP's bus-mastering and memory decoding settings. It is up to the caller to ensure it is already set properly. Change-Id: I7e29a3935df94d16de90b28ff78449d23fe01666 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14	soc/amd/stoneyridge: Load SMU fimware using PSP	Marshall Dawson
	Add the ability to locate the SMRAM-based SMU firmware early and call the PSP library to load it prior to DRAM initialization. This is currently placed in bootblock to ensure the blob is loaded before any reset occurs. Add similar functionality in ramstage for SMU FW2 to the hook already in place for running AmdInitEnv. Rename the hook to make more sense. This patch was tested using a pre-released PSP bootloader on a google/kahlee system. Leave the option unused until the bootloader is ready. BUG=b:66339938 Change-Id: Iedf768e54a7c3b3e7cf07e266a6906923c0fad42 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08	soc/amd/common/psp: Add command to load fw blobs	Marshall Dawson
	An upcoming PSP firmware change will allow coreboot to load the two SMU firmware blobs (one runs in SRAM and the other in DRAM). The traditional method is for the PSP to control most of the process, e.g. loading the SRAM version prior to releasing the x86 reset. Add a new command that can instruct the PSP to load a firmware blob from a location in the flash. The definition for commands 19 and 1a differ from others in that they do not use a command/response buffer. Instead, the PSP will look in the command/response pointer registers directly for the blob's address. BUG=b:66339938 Change-Id: I8431af341930f45ac74f471628b4dc4ede7735f4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-06	soc/amd/common/psp: Require PSP PCI definition in SOC	Marshall Dawson
	Remove the definition for the PSP PCI device from the common PSP code. Any APU using this source should have its own definitions, and this allows for the device to move within the config space. Change-Id: Ie41dfa348b04f655640b4259b1aa518376655251 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16	soc/amd/common: Clean up file includes	Frank Vibrans
	Remove unnecessary header file includes. Change-Id: I9ad9e86f3c75903e278e898602caec04351f64b6 Signed-off-by: Frank Vibrans <frank.vibrans@scarletltd.com> Reviewed-on: https://review.coreboot.org/21989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-02	soc/amd/common: Add initial support for AMD PSP	Marshall Dawson
	Add files for supporting the BIOS->PSP communication not covered by AGESA. The first command implemented notifies the PSP that DRAM is ready. This patch also introduces the amd/common/block directory structure similar to intel/common/block. Change-Id: I34b2744b071aa3dfb1071b2aabde32ddb662ab87 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>