aboutsummaryrefslogtreecommitdiff
path: root/src/soc/amd/common/block/include/amdblocks/acpimmio.h
AgeCommit message (Collapse)Author
2021-02-12soc/amd: add and use fch_enable_hpet_decodeFelix Held
On Picasso we missed setting this bit in coreboot and since the default after reset is 0, we had to rely on the FSP to set this bit. Stoneyridge and Cezanne have the HPET decode enable bit in the same position in the same register. In the ACPI table entry written by southbridge_write_acpi_tables the HPET entry gets added, so we should make sure that we enable the decode. TEST=HPET still works on Mandolin. Change-Id: Ie98dae1d6036748f700f884d4b9653f2e59c24da Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50512 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-12soc/amd/common: add and use fch_enable_ioapic_decodeFelix Held
The default value of this bit is 0, so set it right before calling setup_ioapic to make sure that it's set and not to have to rely on FSP doing the right thing. Change-Id: Ife886451a6927965769282fc5644c2085abb9585 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50513 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-01soc/amd/common: Use only byte access for old GPIOKyösti Mälkki
Change-Id: I06ec29845d051d9b90ab6f3cfb269ad5e6b75ea8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-01soc/amd/common: Drop ACPIMMIO GPIO bank separationKyösti Mälkki
It's assumed in ASL already that the banks appear one after other in ACPIMMIO space. There is no need for the separation of accessor functions by name. Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-16soc/amd/common: Use only byte access for IOMUXKyösti Mälkki
Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42978 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-12soc/amd/common: Remove SMBus host word accessorsKyösti Mälkki
SMBus controller has byte-wide registers. Remove the word accessors. Change-Id: If396108308bc8303d84458039b9529ecd83276c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-12soc/amd/common: Refactor ACPIMMIO posted writesKyösti Mälkki
Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42825 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd: factor out functionality to print last reset sourceFelix Held
Change-Id: I5cec38dac7ea27aa316f5dd4f91ed84627a0f937 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: factor out legacy I/O and cf9 decode enable functionsFelix Held
Replace sb prefix with fch prefix, since those are all FCHs and no south bridges any more. Verstage on PSP uses the I/O access mechanism instead of the MMIO one, so keep a separate function for that, but also move it to the common mmio_util file to have them all in one place. Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48435 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09soc/amd/common/block/smbus: refactor fch_smbus_initFelix Held
Move the setup of the base address to a separate function and explicitly set the SMBUS and ASF I/O port decode even though it is expected to already be set after reset. Change-Id: I8072ab78985021d19b6528100c674ecdd777e62e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: factor out PM_DECODE_EN register definitionsFelix Held
Change-Id: I005709a8780725339e7c08fbfff94e89c8ef26da Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09soc/amd: remove unused PM_ISA_CONTROL definitionsFelix Held
ACPIMMIO_DECODE_REGISTER_04 is the definition in the common ACPIMMIO code block that actually gets used. Also fix the indentation of the ACPIMMIO register decode defines in the common code. Change-Id: Ib2c460541be768fe05d8cc3d19a14dbd9c114a45 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-16soc/amd/common/block: drop double underscores from include guardsFelix Held
Since coreboot is written in C and not C++, having the double underscores as a prefix is not an issue, but it also doesn't add much information, so drop them and the trailing ones as well. Change-Id: I1028fb9097efab8ffae5ffa9fe85a97feebc78a9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47583 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13soc/amd/common/block/include: make include guards more uniformFelix Held
TEST=Timeless build doesn't change for Mandolin and Gardenia. Change-Id: I5d3ae1459c333658f4c86388f1822d92ca13c658 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-29soc/amd/common: Drop ACPIMMIO GPIO bank separationKyösti Mälkki
The banks are one after each other in the ACPIMMIO space. Also there is space for more banks and existing ASL takes advantage of the property. Change-Id: Ib78559a60b5c20d53a60e1726ee2aad1f38f78ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42522 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28soc/amd/common: Allow runtime mapping of ACPIMMIO banksKyösti Mälkki
Future implementation of verstage running on PSP will have access to some of the ACPIMMIO banks, but banks will be mapped runtime at non-deterministic addresses. Provide preprocessor helpers to accomplish this. Change-Id: I8d50de60bb1ea1b3a521ab535a5637c4de8c3559 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2020-06-28soc/amd/common: Access ACPIMMIO via proper symbolsKyösti Mälkki
Using proper symbols for base addresses, it is possible to only define the symbols for base addresses implemented for the specific platform and executing stage. Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-25Revert "soc/amd/common/block/acpimmio: Update acpimmio for psp_verstage"Kyösti Mälkki
This reverts commit 4883252912665f56c8e7801fe03a26594a1e9d5d. Almost everything in <amdblocks/acpimmio_map.h> is invalid for PSP as it does not have the same view of memory space. The prototypes xx_set/get_bar() are only valid for PSP as x86 cores will use the constant mapping defined in <amdblocks/acpimmio_map.h> The selected MMIO base address model depends of the architecture the stage is built for and, to current knowledge, nothing else. So the guards should have been with ENV_X86 vs ENV_ARM and not about CONFIG(VERSTAGE_BEFORE_BOOTBLOCK). For the ENV_ARM stage builds, <arch/io.h> file referenced in the previously added mmio_util_psp.c file has not been added to the tree. So there was some out-of-order submitting, which did not get caught as the build-testing of mixed-arch stages has not been incorporated into the tree yet. The previously added file mmio_util_psp.c is also 90% redundant with mmio_util.c. Change-Id: I1d632f52745bc6cd3c3dbddb1ea5ff9ba962c2e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42486 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15soc/amd/common/block/acpimmio: Update acpimmio for psp_verstageMartin Roth
Because the PSP maps the MMIO addresses that are used to non- deterministic addresses, the accesses need to be able to find the address at runtime. BUG=b:158124527 TEST=Build & boot with Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I68305e0f31956c57bfdee42025bdfe938703e82d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42061 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove redundant includesElyes HAOUAS
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>, <stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes each time when <types.h> is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20soc/amd: replace remaining license headers with SPDX onesFelix Held
Change-Id: Ib45e93faebc2d24389f8739911419dfec437bd59 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-01-03amdblocks/acpimmio: add missing MMIO functionsMichał Żygowski
Add missing Power Management 2, old and new GPIO functions to modify the contents of these MMIO blocks. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie4db6a4d12d9122ea5b87147adbf7b632ac2b311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-03amdblocks/biosram: Force use of abstractionKyösti Mälkki
Hide the fundamental BIOSRAM accessors to force use of the memory space via abstraction functions. Change-Id: I774b6640cdd9873f52e446c4ca41b7c537a87883 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37862 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04soc/amd/common/block/acpimmio: fix ACPIMMIO decode enable functionMichał Żygowski
According to BKDGs for families 15h 60-6fh or newer and families 16h the ACPI MMIO decode enable bit is the second LSB, not the first LSB. Additionally create another enable function for older families where the register and bit is different. It does not seem to impact any current board, but may be crucial for incoming C bootblock implementations when this bit will need to be set very early. Most likely this bit is set by AGESA right now. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37178 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02soc/amd/common: Inline ACPI MMIO accessorsKyösti Mälkki
The overhead of pushing variables to stack exceeded the number of instructions the actual MMIO operation took and the build of google/aleena with inlined accessors turned out to be just slightly (<2 KiB) smaller for the entire romstage or ramstage. Simple read-modify-write MMIO cycles should optimise better now. IO cycles with index/data register are borderline, at first sight assembly looked better by not inlining them. Change-Id: If2c37c9886a0151183aa6dd80eb068d6c67b3848 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-28soc/amd/common: Remove guards on ACPIMMIO utilsKyösti Mälkki
If one wishes to use the functions guarded here, he has to have datasheet open anyways. It should be clear from there which regions are supported and which are not. TEST=Reproducible build of google/aleena. Change-Id: I0c1f0c9c9a6711532c5078c08cdf9e6612f3bc9c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-10-20soc/amd/common: Add AcpiMmio access for SMBus PCI deviceMarshall Dawson
The standard PCI register space for D14F0 is accessible at 0xfed80000. Add functions for use as helpers. Change-Id: Icbf5bdc449322c3f5e59e6126d709cb2808591d5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-06soc/amd/common: Add missing stdint.h to acpimmio.hMarshall Dawson
Include the file containing the typedefs for uint_*. Change-Id: I3eae80a677e9d6932dc115523da2c0819a371fa7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35268 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-11soc/amd/common: Add errors for invalid AcpiMmio accessMarshall Dawson
Add a method for the soc/amd/<product> to indicate what AcpiMmio ranges are supported. Induce a build error if soc or mainboard code is added which attempts to use an unsupported block. This patch attempts to dissuade accessing unsupported blocks without requiring the complexity of structures or reinitializing at the beginning of a new stage. TEST=boot grunt, force build errors by removing blocks in iomap.h BUG=b:131682806 Change-Id: I2121df108fd3caf07e5588bc3201bcdd8dcaaa00 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-06-06soc/amd/common: Update AcpiMmio commentsMarshall Dawson
Document the AcpiMmio individual blocks better. This is in response to a request in gerrit for 69486cac7: Create AcpiMmio functionality from stoneyridge Correct comments that were inadvertently left in place from older patches. Change-Id: I4c16a866de5622e8cfbd3a08816b9d3182950d0e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32931 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Fix consistency in AcpiMmio argumentsMarshall Dawson
Change all arguments named "offset" to "reg" to match the others. These should have gone into change 69486cac7: Create AcpiMmio functionality from stoneyridge Change-Id: Ifdd00d0a5d1e03bfa68a13eeece2d2cfd56aa39d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32930 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/common: Clean up prototypes for AcpiMmioMarshall Dawson
Reorder the biosram prototypes to match the rest of the file. Remove prototypes for asf 32-bit functions that have not been implemented. Change-Id: Ic2663158d8a71952c26eb37f34342a6ea5e58a42 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32929 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-16soc/amd/common: Create AcpiMmio functionality from stoneyridgeMarshall Dawson
Move the stoneyridge AcpiMmio code into soc/amd/common. The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000 commonly known as AcpiMmio. Implementations beginning with Mullins enable decode in PMx04. Older designs use PMx24 and allow for configuring the base address. Future work may support the older version. Comparing the documentation for AMD's RRGs and BKDGs, it is evident that the block locations have not been reassigned across products. In some cases, address locations are deprecated and new ones consumed, e.g. the early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks are now at 0x1500, 0x1600, and 0x1700. Note: Do not infer the definitions within the hardware blocks are consistent across family/model products. BUG=b:131682806 Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-03 04:19:20 +0000