coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-01-28	arch/x86: Top-align .init in bootblock	Kyösti Mälkki
	Link .init section near the end of bootblock program. It contains _start16bit, gdtptr and gdt that must be addressable from realmode, thus within top 64 KiB. Change-Id: If7b9737650362ac7cd82685cfdfaf18bd2429238 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28	cpu/x86: Rename __protected_start symbol	Kyösti Mälkki
	It was confusing to have this defined while there was another symbol bootblock_protected_mode_entry that was not really used as an entry point. Change-Id: I3da07ba9c0a9fc15b1515452adfb27f963659951 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48404 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07	arch/x86: Move prologue to .init section	Kyösti Mälkki
	For arch/x86 the realmode part has to be located within the same 64 KiB as the reset vector. Some older intel platforms also require 4 KiB alignment for _start16bit. To enforce the above, and to separate required parts of .text without matching (.text.) rules in linker scripts, tag the pre-C environment assembly code with section .init directive. Description of .init section for ELF: This section holds executable instructions that contribute to the process initialization code. When a program starts to run, the system arranges to execute the code in this section before calling the main program entry point (called main for C programs). Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16	arch/x86: Clean up bootblock assembly	Kyösti Mälkki
	We have identical gdtptr16 and gdtptr. The reference in gdtptr_offset calculation is not accounted for when considering --gc-sections, so to support linking gdt_init.S separately add dummy use of gdtptr symbol. Realmode execution already accessed gdt that was located outside [_start16bit,_estart16bit] region. Remove latter symbol as the former was not really a start of region, but entry point symbol. With the romcc bootblock solution, entry32.inc may have been linked into romstage before, but the !ENV_BOOTBLOCK case seems obsolete now. Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-11	soc/amd/picasso: factor out write_resume_eip to common code	Felix Held
	Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-09	soc/amd: Remove Kconfig BOOTBLOCK_ADDR	Kyösti Mälkki
	Due the location of X86_RESET_VECTOR, the anchor point for linking the bootblock is at the end, which equals ROMSTAGE_ADDR. Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-09	soc/amd: Remove Kconfig X86_RESET_VECTOR	Kyösti Mälkki
	The architectural requirement is for the address to be located at the end of bootblock -0x10 bytes, so the definition was redundant with other Kconfig variables. Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-06	soc/amd/common/block/cpu: move Makefile guards into subfolders	Felix Held
	The next patch will add a tsc subfolder that might end up containing code that is guarded with different Kconfig options, so move the guards into the Makefiles in the subfolders instead of guarding the inclusion of the Makefiles in the subdirectories with the corresponding Kconfig option. Change-Id: Iafc867eb9adcb23e9a4878cc381684db6f9692d5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05	soc/amd: Fix X86_RESET_VECTOR location in comments	Kyösti Mälkki
	Change-Id: I3e4b3cbed8abe3988d9f48c13d01400af75a4776 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48307 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02	cbfs: Enable CBFS mcache on most chipsets	Julius Werner
	This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-30	soc/amd: move assembly part of non-CAR bootblock to common directory	Felix Held
	There will be more files added to the common non-CAR Makefile.inc, so use an ifeq statement there. Change-Id: I1f71954d27fbf10725387a0e95bc57f5040024cc Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-11-22	soc/amd: move non-CAR linker scripts to common directory	Felix Held
	AMD family 17h and newer don't use cache as RAM, since the RAM is already initialized by the PSP when the x86 cores are released from reset. Therefore they use a different linker script as the rest of the x86 chips in coreboot do. Since there will be support for newer generations than Picasso will be added, move those linker scripts from soc/amd/picasso to soc/amd/common/block/cpu/noncar. TEST=Timeless build of amd/mandolin and amd/gardenia result in identical binaries. Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>