coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-10-02	soc/amd/common: Add framework for missing AGESA callouts	Martin Roth
	These are required callout functions that currently are not implemented. agesa_LateRunApTask does not seem to be called, but the others are. BUG=b:66690176 TEST=Build Kahlee. Tested in next commit. Change-Id: Iee5f9c4847a5309a25045fca8c73be4f811c281a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21707 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27	amd/stoneyridge: Put AGESA heap into cbmem	Marshall Dawson
	Now that soc/amd supports EARLY_CBMEM_INIT, put the HEAP into cbmem, allowing better control of its cacheability in subsequent patches. This relocates the heap initialization from the common directory into a romstage cbmem hook. The conversion relies on cbmem_add() first searching cbmem for the ID before adding a new entry. Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27	soc/amd/common: Clean up GetHeapBase function	Marshall Dawson
	Make GetHeapBase a static function. Change the type of return value to a void pointer and remove the unused StdHeader argument. This should be innocuous and will allow a subsequent patch to be simpler. Change-Id: Id4a024d000a514ea9a44f9dfc2caffae9ff01789 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21593 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-28	soc/amd: Standardize guards on header files	Martin Roth
	The guards in the header files were inconsistent. Some had no leading or trailing underscores, some had one, some had both leading and trailing. Change all to double leading & trailing underscores. Change all comments to have a space before them instead of tabs BUG=b:62235990 Test=Build Kahlee Change-Id: I4466df529ab201c922096a31d7438381778b582f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-27	soc/amd/common: Fix most checkpatch errors	Marshall Dawson
	Correct the majority of reported errors and mark most of the remaining ones as todo. Some of the lines requiring a >80 break are indented too much currently. Changes to agesawrapper.c cause the build to change, so this file is also left as-is. Make hex values consistently lower-case. BUG=chrome-os-partner:622407746 Change-Id: I0464f0cafac4ee67edc95d377dcf7aab9a90c66b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27	vendorcode/amd: Unify Porting.h across all targets	Stefan Reinauer
	This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (agesa_func)(UINT32 Func, UINT32 Data, VOID ConfigPtr) to AGESA_STATUS (agesa_func)(UINT32 Func, UINTN Data, VOID ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-26	soc/amd/stoneyridge: Add northbridge support	Marc Jones
	Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>