coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-04-05	soc/amd/cezanne: Add soc/msr.h	Raul E Rangel
2021-04-05	soc/amd: Make espi_clear_decodes private	Raul E Rangel
2021-04-05	soc/amd: Make espi_configure_decodes private	Raul E Rangel
2021-04-05	soc/amd/cezanne: Clear eSPI ranges before configuring eSPI	Martin Roth
2021-04-02	soc/amd/cezanne: Add support to perform early EC sync	Karthikeyan Ramasubramanian
2021-04-01	soc/amd/cezanne: Enable GENERIC_GPIO_LIB	Raul E Rangel
2021-04-01	soc/amd/cezanne: Add device tree support for I2C	Raul E Rangel
2021-03-30	soc/amd/cezanne: Comment the AOAC register access	Karthikeyan Ramasubramanian
2021-03-29	soc/amd/cezanne: factor out UPD-M configuration from romstage	Felix Held
2021-03-29	soc/amd/cezanne,picasso: rename fsp_params.c to fsp_s_params.c	Felix Held
2021-03-29	soc/amd: add DISABLE_KEYBOARD_RESET_PIN option	Felix Held
2021-03-29	soc/amd/cezanne: Implement PROVIDES_ROM_SHARING	Raul E Rangel
2021-03-29	soc/amd: move PM_RST_CTRL1 register definition to common acpimmio header	Felix Held
2021-03-29	soc/amd/*/gpio: include types.h instead of stdint.h to have size_t	Felix Held
2021-03-24	mb/google/guybrush: disable KBRSTEN	Kangheui Won
2021-03-23	soc/amd/cezanne: select HAVE_EM100_SUPPORT	Felix Held
2021-03-22	soc/amd/cezanne: Initialize I2C	Zheng Bao
2021-03-22	soc/amd/cezanne: Get I2C specific code for cezanne	Zheng Bao
2021-03-18	soc/amd/cezanne/pci_gpp: Add ACPI names for GPP bridges	Raul E Rangel
2021-03-15	soc/amd/cezanne: Add i2c controllers to chipset.cb	Mathew King
2021-03-14	soc/amd/cezanne/Kconfig: turn on GOP	Nikolai Vyssotski
2021-03-13	soc/amd/cezanne/acpi/soc.asl: Include sleepstates.asl	Raul E Rangel
2021-03-13	soc/amd/cezanne/fsp_params.c: GOP: pass VBIOS pointer to FSP	Nikolai Vyssotski
2021-03-13	soc/amd/cezanne: Move globalnvs.asl to the correct location	Mathew King
2021-03-12	soc/amd: GOP: add UPD for VBIOS buffer	Nikolai Vyssotski
2021-03-12	soc/amd/cezanne: add XHCI SCI/GEVENT setup	Felix Held
2021-03-12	soc/amd/common/block/smu: rename mailbox register defines	Felix Held
2021-03-11	soc/amd: move warm reset flag function prototypes to common code	Felix Held
2021-03-10	soc/amd/cezanne: Add USB ports to chipset.cb	Mathew King
2021-03-10	mb/amd/majolica: Update to use proper APCBs built for Majolica	Matt Papageorge
2021-03-10	soc/amd/cezanne: select common APOB NV cache code	Felix Held
2021-03-10	soc/amd/cezanne/smihandler: add ELOG and SMMSTORE support	Felix Held
2021-03-09	soc/amd/cezanne/Makefile: pass APOB NV parameters to amdfwtool	Felix Held
2021-03-08	soc/amd/cezanne: Include gpio.c in smm	Mathew King
2021-03-08	soc/amd/cezanne: Allow GPIO defines to be used in ASL	Mathew King
2021-03-04	soc/amd/cezanne/chipset.cb: clean up and change some aliases	Felix Held
2021-03-04	soc/amd/cezanne/smihandler: implement S3 entry SMI handler	Felix Held
2021-03-04	soc/amd/cezanne: add SMU support	Felix Held
2021-03-03	soc/amd/cezanne/chipset.cb: rename alias for SATA controllers	Felix Held
2021-03-02	soc/amd/cezanne: Disable legacy DMA IO ports	Raul E Rangel
2021-03-02	soc/amd/cezanne: Fill out pci devices in chipset.cb	Mathew King
2021-03-01	soc/amd/cezanne: Add PSP whitelist debug unlock support	Raul E Rangel
2021-02-26	soc/amd/cezanne/acpi: Generate MADT LAPIC NMI settings	Raul E Rangel
2021-02-25	soc/amd/cezanne/acpi: Use IO addresses for ACPI block	Raul E Rangel
2021-02-25	soc/amd/cezanne/acpi: Add globalnvs.asl	Raul E Rangel
2021-02-25	soc/amd: only print CPU family and model in bootblock	Felix Held
2021-02-25	soc/amd/cezanne/Kconfig: sort selected options	Felix Held
2021-02-25	soc/amd/cezanne/acpi/pci0.asl: Add LPC device	Raul E Rangel
2021-02-24	soc/amd/cezanne: Add eSPI support	Zheng Bao
2021-02-24	soc/amd/cezanne/Makefile: move setting of PSP soft fuse bit 6	Felix Held
2021-02-22	soc/amd/cezanne/acpi: Add pci0.asl	Raul E Rangel
2021-02-22	soc/amd/cezanne/acpi/soc.asl: Add platform.asl	Raul E Rangel
2021-02-22	soc/amd/cezanne/acpi: Add MMIO devices	Raul E Rangel
2021-02-19	soc/amd/cezanne: add MP init and SMM initialization	Felix Held
2021-02-18	soc/amd/cezanne/root_complex: provide ACPI name in PCI device_operations	Felix Held
2021-02-18	soc/amd/cezanne/chip: add soc_acpi_name	Felix Held
2021-02-17	soc/amd/cezanne: Add FCH IO-APIC to MADT	Raul E Rangel
2021-02-17	soc/amd/cezanne/pcie_gpp: add pci_driver for external root ports	Felix Held
2021-02-17	soc/amd/cezanne/pcie_gpp: replace PCI ID list with single PCI ID	Felix Held
2021-02-17	soc/amd/cezanne/uart: write ACPI tables	Felix Held
2021-02-16	soc/amd/cezanne: Enable ACPI_SOC_NVS	Raul E Rangel
2021-02-16	soc/amd/cezanne/data_fabric: add ACPI names and SSDT entries	Felix Held
2021-02-15	soc/amd/cezanne: Add uart.c to smm so we can support DEBUG_SMI	Raul E Rangel
2021-02-14	soc/amd/cezanne: add partial data fabric setup	Felix Held
2021-02-14	soc/amd/cezanne/include/iomap: add HPET base address	Felix Held
2021-02-14	soc/amd/cezanne/chipset.cb: add SMBus and data fabric PCI devices	Felix Held
2021-02-14	soc/amd/cezanne: move CPU cluster to chipset device tree	Felix Held
2021-02-14	soc/amd/cezanne: Fill FADT and MADT	Raul E Rangel
2021-02-14	soc/amd/cezanne: Enable uCode update	Raul E Rangel
2021-02-13	soc/amd/cezanne: select ACPI support and make the compiler happy	Felix Held
2021-02-13	soc/amd/cezanne/acpi: Add plain soc.asl	Raul E Rangel
2021-02-13	soc/amd/cezanne: always include PSP secure OS in amdfw	Felix Held
2021-02-13	soc/amd/cezanne: always add S0i3 firmware part to amdfw	Felix Held
2021-02-13	soc/amd/cezanne/bootblock: call write_resume_eip in bootblock_c_entry	Felix Held
2021-02-12	soc/amd/cezanne: drop PWRS from GNVS	Felix Held
2021-02-12	soc/amd/cezanne: Add PCI IRQ Router definitions	Raul E Rangel
2021-02-12	soc/amd/cezanne/smihandler: add psp_notify_smm call	Felix Held
2021-02-12	soc/amd/cezanne: select RTC	Felix Held
2021-02-12	soc/amd: select ACPI_AMD_HARDWARE_SLEEP_VALUES in common ACPI code	Felix Held
2021-02-12	soc/amd/*/Kconfig: remove redundant SMM_TSEG condition	Felix Held
2021-02-11	soc/amd/cezanne/smihandler: add basic SMI APMC and sleep handler	Felix Held
2021-02-11	soc/amd/cezanne: select soc-specific ACPI functionality	Felix Held
2021-02-11	soc/amd/cezanne/chip: set device operations for UART MMIO devices	Felix Held
2021-02-11	soc/amd/cezanne: add empty mp_init_cpus	Felix Held
2021-02-11	soc/amd/cezanne/cpu: add basic zen_2_3_init functionality	Felix Held
2021-02-11	soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handler	Felix Held
2021-02-11	soc/amd: include cpu/x86/smm directory in common SMM Makefile	Felix Held
2021-02-11	soc/amd: move southbridge_smi_handler to common code	Felix Held
2021-02-11	soc/amd: factor out common SMM relocation code	Felix Held
2021-02-11	soc/amd/cezanne: add empty SMM-handler	Felix Held
2021-02-10	soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports	Felix Held
2021-02-10	soc/amd/cezanne: Add verstage support	Raul E Rangel
2021-02-10	soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI	Raul E Rangel
2021-02-10	soc/amd/cezanne: Add SPI registers	Raul E Rangel
2021-02-10	soc/amd/cezanne/chip: add empty set_mmio_dev_ops	Felix Held
2021-02-10	soc/amd/cezanne/chip: add empty cpu_bus_ops	Felix Held
2021-02-10	soc/amd: Move soc_route_sci to common/blocks/smi/smi_util	Felix Held
2021-02-09	soc/amd/cezanne: Add root_complex	Raul E Rangel
2021-02-09	soc/amd/cezanne: add empty CPU driver	Felix Held
2021-02-09	soc/amd/cezanne: Enable early LPC support in bootblock stage	Zheng Bao