coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-03-09	soc/amd/cezanne: Update XHCI GPE to use constant	Robert Zieba
	The GPE number used for XHCI has now been defined in AMD's common code in CB:67936. Change over existing code to use this new definition. BRANCH=guybrush BUG=b:186792595 TEST=Ran on nipperkin device and verified that XHCI events string use GPE 31. Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I9c2a44f7d2eb47422ae8c585e5e01ea0b420d461 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69917 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23	soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h	Felix Held
	This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-12	soc/amd/cezanne: add XHCI SCI/GEVENT setup	Felix Held
	Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I32fd9b7165306266613e8497b5d07473b5fea02d Reviewed-on: https://review.coreboot.org/c/coreboot/+/51415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>