coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-06-11	soc/amd/cezanne: remove warm reset flag code	Felix Held
	The warm reset bit in the NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if something was written to the register, the NCP_WARM_BOOT bit never got set and the NCP_ERR register in I/O-space always reads back as 0x7f. [1] checked with PPR for AMD Family 19h Model 51h A1 (CZN) #56569 Rev 3.01 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55101 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-22	soc/amd/cezanne,picasso/reset: use byte I/O read for NCP_ERR	Felix Held
	NCP_ERR is a 1 byte register in I/O-space, so use inb and not inw. The variable the result gets assigned to is also a uint8_t. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9fd8c139004111d6227c0316ba2a8b0281541654 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-10	soc/amd/cezanne: Force resets to be cold	Marshall Dawson
	Cezanne must use cold resets. Change the warm reset request to always set TOGGLE_ALL_PWR_GOOD. And, since the bit is sticky across power cycles, set it early for good measure. BUG=b:184281092 TEST=Majolica successfully resets using 0xcf9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-11	soc/amd: move warm reset flag function prototypes to common code	Felix Held
	Even though the implementation is different on Stoneyridge compared to Picasso and Cezanne, the function prototypes are identical, so move them to the AMD SoC common reset header file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-11	soc/amd/cezanne: add 0xcf9 reset	Felix Held
	Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>