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path: root/src/soc/amd/cezanne/include
AgeCommit message (Expand)Author
2021-02-10soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_portsFelix Held
2021-02-10soc/amd/cezanne: Add SPI registersRaul E Rangel
2021-02-09soc/amd/cezanne: Enable early LPC support in bootblock stageZheng Bao
2021-02-05soc/amd/cezanne/iomap: move MMIO range comment above MMIO rangesFelix Held
2021-02-05soc/amd/cezanne/fch: add ACPI I/O port setupFelix Held
2021-02-03soc/amd/cezanne: remove UART2/3 AOAC device offsetsFelix Held
2021-01-31soc/amd/cezanne: add soc/cpu.h with CPUID define for Cezanne A0 steppingFelix Held
2021-01-29soc/amd/cezanne: add empty ramstage FCH supportFelix Held
2021-01-22soc/amd/cezanne: add pci_devs.hFelix Held
2021-01-14soc/amd/cezanne: add AOAC supportFelix Held
2021-01-14soc/amd/cezanne: add console UART supportFelix Held
2020-12-18soc/amd/cezanne: Add SMI supportZheng Bao
2020-12-17soc/amd/cezanne: add GPIO definitionsFelix Held
2020-12-13soc/amd/cezanne: add caching setup in bootblockFelix Held
2020-12-11soc/amd/cezanne: add 0xcf9 resetFelix Held
2020-12-09soc/amd/cezanne: add basic early FCH initialization to bootblockFelix Held
2020-12-09soc/amd/cezanne: add common SMBus code to buildFelix Held
2020-12-05soc/amd/cezanne: add skeleton for new SoCFelix Held