coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-01-20	soc/amd/cezanne/include/espi.h: add missing include guards	Felix Held
2022-01-14	soc/amd/cezanne: factor out eSPI SPI2 pads configuration functions	Felix Held
2022-01-11	soc/amd/cezanne/include/i2c: add missing types.h include	Felix Held
2022-01-11	soc/amd/cezanne/include/i2c: move include inside header guard	Felix Held
2021-12-20	soc/amd/cezanne/fch: disable 48MHz output in S0i3	Felix Held
2021-11-30	soc/amd/cezanne: add missing PM_ACPI_* bit definitions	Felix Held
2021-11-25	soc/amd/*/data_fabric: use DF_ prefix for bit and shift defines	Felix Held
2021-11-25	soc/amd/*/include/data_fabric: make MMIO_NP definition SoC-specific	Felix Held
2021-11-10	soc/amd/cezanne,picasso/include/southbridge: use bitwise or in defines	Felix Held
2021-11-09	soc/amd/cezanne,picasso/include/southbridge: fix typo in define	Felix Held
2021-11-05	soc/amd/*/include/smi: move NUMBER_SMITYPES definition to the top	Felix Held
2021-11-05	soc/amd/*/include/smi: fix off-by-one in SCIMAPS defines	Felix Held
2021-11-04	soc/amd/cezanne/include/gpio: fix GPIO 106 native function names	Felix Held
2021-11-04	soc/amd/cezanne/include/cppc: use AMD_CEZANNE_CPPC_H as include guard	Felix Held
2021-11-03	soc/amd/cezanne/include/aoac_defs: drop leading newline	Felix Held
2021-11-03	soc/amd/cezanne/include: replace PICASSO with CEZANNE in include guards	Felix Held
2021-11-02	psp_verstage: convert relative address in EFS2	Kangheui Won
2021-10-21	acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table	Michael Niewöhner
2021-10-15	soc/amd/common/block/i2c: implement proper read_resource	Felix Held
2021-10-13	src/soc/amd/cezanne: enable clock gating	Julian Schroeder
2021-10-13	soc/amd/common/block/espi_util: Refactor eSPI Setup	Karthikeyan Ramasubramanian
2021-10-11	soc/amd/cezanne/include/southbridge: add some more PM register defines	Felix Held
2021-10-11	soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits	Felix Held
2021-09-23	soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h	Felix Held
2021-09-09	soc/amd/cezanne/include/gpio: add remote GPIO pin mux definitions	Felix Held
2021-08-31	soc/amd/*/include/soc/gpio: remove GPIO_2_EVENT	Felix Held
2021-08-30	soc/amd/cezanne/fch: implement and use fch_clk_output_48Mhz	Felix Held
2021-07-17	soc/amd/cezanne/graphics: add VBIOS ID remapping for Barcelo	Felix Held
2021-07-15	soc/amd/cezanne: add ACPI CPPC support for AMD	Julian Schroeder
2021-07-14	soc/amd: move check_mca prototype to soc/amd/common/blocks/include	Felix Held
2021-07-14	soc/amd/cezanne: add basic MCA support	Felix Held
2021-06-23	soc/amd/cezanne: Init eSPI early if required	Martin Roth
2021-06-16	soc/amd/cezanne/include/soc/iomap: add eMMC MMIO base addresses	Felix Held
2021-06-16	soc/amd/cezanne,picasso/include/soc/iomap: reflow I2C_DEVICE_COUNT	Felix Held
2021-06-16	soc/amd/cezanne: factor out AOAC offset defines	Felix Held
2021-06-16	soc/amd/cezanne,picasso: add AOAC offset define for the eMMC controller	Felix Held
2021-06-11	soc/amd/cezanne: remove warm reset flag code	Felix Held
2021-06-01	soc/amd/cezanne/include/iomap: properly align defines	Felix Held
2021-05-31	soc/amd/cezanne: Add pre-FSPM call to the mainboard	Martin Roth
2021-05-19	soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settings	Felix Held
2021-05-10	cezanne/psp_verstage: update SRAM address	Kangheui Won
2021-05-09	soc/amd/cezanne: add GNB IOAPIC support	Felix Held
2021-05-05	soc/amd/cezanne/agesa_acpi: add and call agesa_write_acpi_tables	Felix Held
2021-05-02	soc/amd/cezanne: add verstage files	Kangheui Won
2021-04-28	soc/amd/cezanne: copy psp_transfer.h from picasso	Kangheui Won
2021-04-23	soc/amd/cezanne: fix i2c compiler errors on non-x86	Kangheui Won
2021-04-07	soc/amd/cezanne: Pass DXIO and DDI Descriptors to FSP	Matt Papageorge
2021-04-05	soc/amd/cezanne: Add soc/msr.h	Raul E Rangel
2021-03-29	soc/amd: move PM_RST_CTRL1 register definition to common acpimmio header	Felix Held
2021-03-24	mb/google/guybrush: disable KBRSTEN	Kangheui Won
2021-03-22	soc/amd/cezanne: Get I2C specific code for cezanne	Zheng Bao
2021-03-12	soc/amd/common/block/smu: rename mailbox register defines	Felix Held
2021-03-11	soc/amd: move warm reset flag function prototypes to common code	Felix Held
2021-03-08	soc/amd/cezanne: Allow GPIO defines to be used in ASL	Mathew King
2021-03-04	soc/amd/cezanne: add SMU support	Felix Held
2021-02-22	soc/amd/cezanne/acpi: Add MMIO devices	Raul E Rangel
2021-02-14	soc/amd/cezanne: add partial data fabric setup	Felix Held
2021-02-14	soc/amd/cezanne/include/iomap: add HPET base address	Felix Held
2021-02-14	soc/amd/cezanne: Fill FADT and MADT	Raul E Rangel
2021-02-12	soc/amd/cezanne: drop PWRS from GNVS	Felix Held
2021-02-12	soc/amd/cezanne: Add PCI IRQ Router definitions	Raul E Rangel
2021-02-11	soc/amd/cezanne: select soc-specific ACPI functionality	Felix Held
2021-02-10	soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports	Felix Held
2021-02-10	soc/amd/cezanne: Add SPI registers	Raul E Rangel
2021-02-09	soc/amd/cezanne: Enable early LPC support in bootblock stage	Zheng Bao
2021-02-05	soc/amd/cezanne/iomap: move MMIO range comment above MMIO ranges	Felix Held
2021-02-05	soc/amd/cezanne/fch: add ACPI I/O port setup	Felix Held
2021-02-03	soc/amd/cezanne: remove UART2/3 AOAC device offsets	Felix Held
2021-01-31	soc/amd/cezanne: add soc/cpu.h with CPUID define for Cezanne A0 stepping	Felix Held
2021-01-29	soc/amd/cezanne: add empty ramstage FCH support	Felix Held
2021-01-22	soc/amd/cezanne: add pci_devs.h	Felix Held
2021-01-14	soc/amd/cezanne: add AOAC support	Felix Held
2021-01-14	soc/amd/cezanne: add console UART support	Felix Held
2020-12-18	soc/amd/cezanne: Add SMI support	Zheng Bao
2020-12-17	soc/amd/cezanne: add GPIO definitions	Felix Held
2020-12-13	soc/amd/cezanne: add caching setup in bootblock	Felix Held
2020-12-11	soc/amd/cezanne: add 0xcf9 reset	Felix Held
2020-12-09	soc/amd/cezanne: add basic early FCH initialization to bootblock	Felix Held
2020-12-09	soc/amd/cezanne: add common SMBus code to build	Felix Held
2020-12-05	soc/amd/cezanne: add skeleton for new SoC	Felix Held