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Add I2C initialization in romstage and ramstage.
TEST=To test the I2C connection on Majolica, which doesn't have SPD
connection, call the function below after i2c_soc_init is called.
i2c_read_bytes(2, 0x4d, addr, data, 1);/* Read out 1 byte one time */
It can get the register values of TMP432B.
Or
/* Override EC port in ec.h */
#define EC_DATA 0x662
#define EC_SC 0x666
ec_write(0xA9, 0x40);
i2c_read_bytes(1, 0x10, addr, data, 2);/* Read out 2 bytes one time */
It can get the register values of CM32181A3OP(ALS).
Change-Id: I3a2a1494b44b68e8d8204fba0c90e769e0256e6f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51029
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These definitions were identical to picasso. The only thing I changed
was that I renamed Misc1 and Misc2 to HPET_L and HPET_H.
This change still doesn't write the PCI_IRQ register for all the PCI
devices. We need to refactor the picasso pci_gpp code first.
TEST=Boot majolica and see FCH IRQs being programmed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic7e637f234d3af426959a9bbd82a0dcf25bb3c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50451
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50454
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from
the reference code, but not the PPR. I've submitted a change request for
the PPR, so this mismatch might go away in the future. The case for
HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends
up being identical to the function in soc/amd/picasso, I'll move it to
the common AMD SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38c6961b65b89cb57ff80e491bf8973be4e12eeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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