Age | Commit message (Expand) | Author |
2023-02-04 | soc/amd: Use common reset code for CZN & MDN SoCs | Martin Roth |
2023-01-17 | treewide: Fix old-style declarations | Elyes Haouas |
2022-10-26 | soc/amd/cezanne: Update GPP clk req code to use ARRAY_SIZE | Robert Zieba |
2022-10-26 | soc/amd/cezanne: Factor out common GPP clk req code | Robert Zieba |
2022-03-23 | soc/amd/cezanne: Turn off gpp clock request for disabled devices | Robert Zieba |
2021-12-20 | soc/amd/cezanne/fch: disable 48MHz output in S0i3 | Felix Held |
2021-12-08 | soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resume | Raul E Rangel |
2021-10-13 | src/soc/amd/cezanne: enable clock gating | Julian Schroeder |
2021-10-05 | src/soc to src/superio: Fix spelling errors | Martin Roth |
2021-09-23 | soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h | Felix Held |
2021-08-30 | soc/amd/cezanne/fch: implement and use fch_clk_output_48Mhz | Felix Held |
2021-05-19 | soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settings | Felix Held |
2021-05-10 | soc/amd/cezanne: Force resets to be cold | Marshall Dawson |
2021-05-09 | soc/amd/cezanne: Populate PCI_INTR registers | Raul E Rangel |
2021-04-14 | soc/amd/cezanne/fch: process ACPI PM/GPE and GPIO events | Felix Held |
2021-03-22 | soc/amd/cezanne: Initialize I2C | Zheng Bao |
2021-02-12 | soc/amd/cezanne: Add PCI IRQ Router definitions | Raul E Rangel |
2021-02-10 | soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports | Felix Held |
2021-02-05 | soc/amd/cezanne/fch: add ACPI I/O port setup | Felix Held |
2021-01-29 | soc/amd/cezanne: add empty ramstage FCH support | Felix Held |