| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-08-30 | soc/amd/cezanne/fch: implement and use fch_clk_output_48Mhz | Felix Held |
| 2021-05-19 | soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settings | Felix Held |
| 2021-05-10 | soc/amd/cezanne: Force resets to be cold | Marshall Dawson |
| 2021-05-09 | soc/amd/cezanne: Populate PCI_INTR registers | Raul E Rangel |
| 2021-04-14 | soc/amd/cezanne/fch: process ACPI PM/GPE and GPIO events | Felix Held |
| 2021-03-22 | soc/amd/cezanne: Initialize I2C | Zheng Bao |
| 2021-02-12 | soc/amd/cezanne: Add PCI IRQ Router definitions | Raul E Rangel |
| 2021-02-10 | soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports | Felix Held |
| 2021-02-05 | soc/amd/cezanne/fch: add ACPI I/O port setup | Felix Held |
| 2021-01-29 | soc/amd/cezanne: add empty ramstage FCH support | Felix Held |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |