| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-02-12 | soc/amd/cezanne: Add PCI IRQ Router definitions | Raul E Rangel |
| 2021-02-10 | soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports | Felix Held |
| 2021-02-05 | soc/amd/cezanne/fch: add ACPI I/O port setup | Felix Held |
| 2021-01-29 | soc/amd/cezanne: add empty ramstage FCH support | Felix Held |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |