coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-02-09	soc/amd/cezanne: Enable early LPC support in bootblock stage	Zheng Bao
	Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-14	soc/amd/cezanne: add AOAC support	Felix Held
	Change-Id: I9d7574b60640eaf9a47a797e823324edeaf1e770 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-14	soc/amd/cezanne: add console UART support	Felix Held
	Change-Id: I1a01cc745c7049dc672bca12df5c6b764ac9b907 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-09	soc/amd/cezanne: add basic early FCH initialization to bootblock	Felix Held
	Change-Id: I1c6d32a5498a7adcee3c8c3145f85e9dba26bf7e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>