coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-02-16	soc/amd/cezanne/data_fabric: add ACPI names and SSDT entries	Felix Held
	Additionally to the PCI IDs of Cezanne it also handles the Renoir ones. The main difference between those two is that Renoir has two core complexes while Cezanne only has one core complex. I haven't seen incompatible changes between those two though, so for example the fabric IDs are the same and the one that's only present in Renoir is just not used in Cezanne. Also adding the ACPI parts for those don't have anything to do with those differences. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b2517bc15d872f41183a33857333f1972ff2cb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-14	soc/amd/cezanne: add partial data fabric setup	Felix Held
	I'm not 100% sure yet if this code will be common for all AMD SoCs, so I'll add a copy for Cezanne for now. This part of the code should probably be reworked after the initial bringup of Cezanne anyway. DF MMIO register configuration at the beginning of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 a3 fc00 febf 1 a3 1000000 fffcffff 2 a3 d000 f7ff 3 a0 0 0 4 a3 fed0 fed0 5 a0 0 0 6 a0 0 0 7 a0 0 0 DF MMIO register configuration at the end of data_fabric_set_mmio_np: === Data Fabric MMIO configuration registers === Addresses are shifted to the right by 16 bits. idx control base limit 0 a3 fc00 febf 1 a3 1000000 fffcffff 2 a3 d000 f7ff 3 10a3 fed0 fedf 4 a0 0 0 5 a0 0 0 6 a0 0 0 7 a0 0 0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia243a0cad311eb210d14d6242c52f599db22515c Reviewed-on: https://review.coreboot.org/c/coreboot/+/50624 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>