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path: root/src/soc/amd/cezanne/chip.h
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2022-10-26soc/amd/cezanne: Factor out common GPP clk req codeRobert Zieba
Factor out the `gpp_dxio_update_clk_req_config` function as it will be useful for other AMD SoCs. BUG=b:250009974 TEST=Ran on nipperkin device, verified clk req settings match enabled devices Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15amd/cezanne: Control DPTC with only KconfigTim Van Patten
SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any guybrush boards, similar to .mainboard/google/zork/Kconfig This makes the value dptc_tablet_mode_enable redundant. This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC is only included for boards that actually enable it. BRANCH=none BUG=b:217911928 TEST=emerge-guybrush coreboot Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I07f1266fa80a6c9ee4ec3b3ba970a70c6c72fb54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-12soc/amd: Remove unsupported DPTC tablet mode settingsTim Van Patten
The following boards are setting DTPC tablet mode values without corresponding device tree values, meaning they are effectively setting "random" values for tablet mode: 1. Cezanne 2. Mendocino The device tree has tablet mode disabled, so the code should never be exercised, but this CL removes it entirely to cleanup "dead" code. BRANCH=none BUG=b:217911928 TEST=Build nipperkin TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ide96f255b69670d1b4c37ca2f94cc3504a958b57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-12soc/amd: Refactor DPTC Tablet ModeTim Van Patten
Refactor AMD DPTC tablet mode in preparation for adding low/no battery DPTC settings. 1. Refactor and simplify acpigen_write_alib_dptc() into the following functions: - acpigen_write_alib_dptc_default() - acpigen_write_alib_dptc_tablet() 2. Add device tree register value dptc_tablet_mode_enable to control whether DPTC tablet mode is enabled for a variant. 3. Add dptc.asl to perform the necessary ACPI checking before modifying the DPTC settings. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build nipperkin TEST=Boot skyrim Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-07amd: Convert dptc_enable to boolTim Van Patten
dptc_enable is being treated as a bool, so convert to explicitly be a bool. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build guybrush TEST=Build skyrim Change-Id: I0e93d892b3b8016221812c8b9ec6c257dcf13ef5 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67188 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23soc/amd/cezanne: Turn off gpp clock request for disabled devicesRobert Zieba
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled, checked that physically removing a device that is marked as enabled also disables the corresponding clk req BRANCH=guybrush Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-03soc/amd/*/i2c: factor out common I2C pad configurationFelix Held
The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-25soc/amd/cezanne: FSP: Add UPD entry for eDP tuningZheng Bao
The FSP gets these values from the UPD and sets the internal values. The document about eDP tuning is attached in issue tracker of this ticket, at the issue tracker b/203061533#comment6. BUG=b:203061533 Cq-Depend: chrome-internal:4303901 Change-Id: I9b85faac4f2fa1fb2c14bb85b615346d4379baac Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-13soc/amd/*/chip.h: add missing gpio.h includeFelix Held
Since we need the GPIO defines in the devicetree settings, include gpio.h in each SoC's chip.h file which will indirectly include the soc-specific soc/gpio.h header instead of having it indirectly included via soc/i2c.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id26721a6b8ae94784d4a90d7ccac28fef2be36dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-07-24soc/amd/*/chip.h: Correct PSPP Enum ValueMatt Papageorge
It appears the pspp_policy enum is not the same as the FSP definition currently being used. This means that the incorrect PSPP value setting would get read by FSP. For Zork programs this meant we actually were setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE. This change adds DXIO_PSPP_DISABLED as the first enum value to properly match the FSP definition and adjusts non AMD Customer Reference Boards that reference the enum to still send the same value even though it has now change definitions. If we actually want DXIO_PSPP_POWERSAVE for those boards that can be adjusted in a future change. BUG=b:193495634 TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi with other server on local network. Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-06-07soc/amd/cezanne: Configure I2C Pad RX Select through devicetreeKarthikeyan Ramasubramanian
Some of the I2C buses are required to operate at different voltage level compared to other I2C buses eg. I2C bus to Google Security Chip (GSC) should be at 1.8V level. By default, all the I2C buses are initialized to operate at 3.3 V. Add support to configure I2C pad RX select through devicetree and update the concerned devicetree. BUG=b:188538373 TEST=Build and boot to OS in Guybrush. Ensure that the communication with GSC is fine. Build Majolica mainboard. Change-Id: I595a64736fdac0274abffb68c5e521302275b845 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-27soc/amd/cezanne: add devicetree setting for PSPP policyFelix Held
This allows boards to specify which PSPP policy (basically a dynamic trade-off between power consumption and PCIe link speed) should be used and also makes sure that the boards are using the expected PSPP policy and not just the UPD default from the FSP binary that has already changed once during the development. BUG=b:188793754 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1b6459b2984711e72b79f5d4d90e04cb4b78d512 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54930 Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-26soc/amd/cezanne: add support for the changed AMD FSP API for USB PHYJulian Schroeder
The AMD FSP is using a new structure for USB and USB C phy settings. This patch removes old, unused structures, adds the new one and enables the devicetree interface for it. Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b Reviewed-on: https://review.coreboot.org/c/coreboot/+/54065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-05-19soc/amd/cezanne/fch: add PCIe GPP clock generator configuration settingsFelix Held
I'm not 100% sure if this should rather be duplicated from Picasso or commonized. Checked with the docs and this won't be compatible with Stoneyridge and one future product's PPR lacked the corresponding register. Some other chip has a compatible register layout, but a different number of PCIe GPP clock outputs, so the common code would need to use some SoC-dependent defines and possibly a SoC-specific lookup table for the mapping which is also not that great. TEST=Checked Cezanne PPR Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b6d0cb8d7eb0288d8a18fcb975dc377b2c6846a Reviewed-on: https://review.coreboot.org/c/coreboot/+/54685 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-12soc/amd/cezanne/chip.h: add DPTC and tablet mode optionsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I39218b79a79f1ccaf1a58408c6bb5161acea64aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/54073 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-30amd/cezanne: Add telemetry setting to UPDChris Wang
Add telemetry setting to UPD, the value comes from the SDLE testing. BUG=b:182754399 TEST=Build & Boot guybrush Cq-Depend: chrome-internal:3787638 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I9dd3643e9c582a41192130901935eef321b2c67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52733 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26soc/amd/cezanne: Update STAPM vars with unitsMartin Roth
Like the Picasso platform, it's very useful to have units on these variables. BUG=b:185209734 TEST=Build & Boot Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I592c807c5e9a2c17b1c5959e56a01237352c5204 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26amd/cezanne: Add slow_ppt_time & thermctl_limit to UPDMartin Roth
These values will be added in the upcoming STAPM configuration update. BUG=b:185209734 TEST=Build & Boot guybrush Cq-Depend: chrome-internal:3780259 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2a6835c16badfe505e3c33b356ca671766cd6972 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-21soc/amd/cezanne: add SMU settings to devicetreeFelix Held
BUG=b:182297189 TEST=none Cq-Depend: chrome-internal:3772425 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifbcc85cc10d59f1418bbf0ed4a0dc7549d589a26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-21soc/amd/cezanne: add downcoring and SMT disable settings to devicetreeFelix Held
BUG=b:184162768 TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id03454ed2be242bce9497560c089f75046ed7e32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52197 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21soc/amd/cezanne/chip.h: include missing types.hFelix Held
Since we use uintX_t, bool and friends, we need to make sure to include the corresponding definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icb8a6e93d7f1923ac95e584fb3e33c391963f5ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/52551 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16soc/amd/cezanne: Add modern standby option to chip configMathew King
BUG=b:178728116 Change-Id: I0d09bd4361f5f47360daf750efbc993010804902 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-22soc/amd/cezanne: Get I2C specific code for cezanneZheng Bao
Add macros, settings and callbacks to support I2C for cezanne. Change-Id: Ic480681d4b7c6fb8591e729090e4faeb5fccf800 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-06soc/amd/cezanne: add config.c and minimal chip.hFelix Held
Change-Id: I89f08c201bd7d9a11b186ef960abe9714a76fb97 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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