| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-02-14 | soc/amd/cezanne: add partial data fabric setup | Felix Held |
| 2021-02-11 | soc/amd/cezanne/chip: set device operations for UART MMIO devices | Felix Held |
| 2021-02-11 | soc/amd/cezanne: add empty mp_init_cpus | Felix Held |
| 2021-02-10 | soc/amd/cezanne/chip: add empty set_mmio_dev_ops | Felix Held |
| 2021-02-10 | soc/amd/cezanne/chip: add empty cpu_bus_ops | Felix Held |
| 2021-02-09 | soc/amd,intel: Drop s3_resume parameter on FSP-S functions | Kyösti Mälkki |
| 2021-02-07 | soc/amd/cezanne/chip: add PCI bus scanning | Felix Held |
| 2021-01-30 | soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls | Felix Held |
| 2021-01-29 | soc/amd/cezanne: add empty ramstage FCH support | Felix Held |
| 2021-01-29 | soc/amd/cezanne/chip: add FSP silicon init driver call | Felix Held |
| 2021-01-28 | soc/amd/cezanne/chip: add empty SoC device operations | Felix Held |
| 2020-12-06 | soc/amd/cezanne: add config.c and minimal chip.h | Felix Held |
| 2020-12-05 | soc/amd/cezanne: add skeleton for new SoC | Felix Held |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |