| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-01-30 | soc/amd/cezanne: add use result of acpi_is_wakeup_s3() in FSP calls | Felix Held |
| 2021-01-29 | soc/amd/cezanne: add empty ramstage FCH support | Felix Held |
| 2021-01-29 | soc/amd/cezanne/chip: add FSP silicon init driver call | Felix Held |
| 2021-01-28 | soc/amd/cezanne/chip: add empty SoC device operations | Felix Held |
| 2020-12-06 | soc/amd/cezanne: add config.c and minimal chip.h | Felix Held |
| 2020-12-05 | soc/amd/cezanne: add skeleton for new SoC | Felix Held |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |