coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-04-21	soc/amd/{cezanne,common}/acpi: Add _OSC method	Raul E Rangel
	The linux kernel requires a valid _OSC method. Otherwise the _LPI table is ignored. See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/acpi/bus.c;l=324 Before this patch: acpi_processor_get_lpi_info: LPI is not supported After this patch: acpi_processor_evaluate_lpi: ACPI: \_SB_.CP00: ACPI: Found 4 power states BUG=b:178728116 TEST=Boot OS and verify _LPI table is parsed Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I44e554b9db6f70fdd1559105cdaee53aeb2bfbf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-20	soc/amd/{common,cezanne}: Add uPEP device	Raul E Rangel
	The uPEP device is required to support S0i3. The device has been written in ASL to make it easier to read and maintain. The device constraints are purely informational. We use a dummy constraint like the Intel platforms to keep both linux and Windows functional. In order for this device to be used by the linux kernel the ACPI_FADT_LOW_PWR_IDLE_S0 flag must be set. So including it unconditionally doesn't cause any problems. The AMD Modern Standby BIOS Implementation Guide defines two UUIDs, one for getting the device constraints, and one for handling notifications. This differs from the Intel specification and the linux driver implementation. For this reason I haven't implemented any of the notification callbacks yet. BUG=b:178728116 TEST=Boot OS and verify _DSM is called: [ 0.226701] lps0_device_attach: ACPI: \_SB_.PEP_: _DSM function mask: 0x3 [ 0.226722] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: _DSM function 1 eval successful [ 0.226723] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list begin: [ 0.226724] lpi_device_get_constraints_amd: ACPI: \_SB_.PEP_: LPI: constraints list end Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2deef47eabe702efe1a0f3747c9f27bcec37464b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52445 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-30	soc/amd/cezanne: Comment the AOAC register access	Karthikeyan Ramasubramanian
	Causing the AOAC register access as part of system suspend (S3) causes the suspend procedure to be stuck. Comment it for now to unblock entering S3 and collecting the power numbers. BUG=b:181766974 TEST=Build and boot to OS in Majolica. Enter S3 through "echo mem > /sys/power/state". Change-Id: Ie93bbe393b209b784b9a2257f3916b29d84b25d1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51926 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13	soc/amd/cezanne/acpi/soc.asl: Include sleepstates.asl	Raul E Rangel
	Needed to get the _SX ASL methods. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6323ba413a21d9d867727dbb28340e6df807c86a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13	soc/amd/cezanne: Move globalnvs.asl to the correct location	Mathew King
	BUG=b:180507937 TEST=guybrush builds without globalnvs in dsdt.asl Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: I3ffe94f7b575126e61245bed9c9560313df2d725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51291 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-25	soc/amd/cezanne/acpi: Add globalnvs.asl	Raul E Rangel
	Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I53290226012d9f6c08c6adae0a633c7fd5702135 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-02-25	soc/amd/cezanne/acpi/pci0.asl: Add LPC device	Raul E Rangel
	Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22	soc/amd/cezanne/acpi: Add pci0.asl	Raul E Rangel
	This differs slightly from picasso. The PCI BAR region is between TOM1 and CONFIG_MMCONF_BASE_ADDRESS. This matches what the Intel platforms are doing. It also matches what linux derives from the e820 tables: > [mem 0xd0000000-0xf7ffffff] available for PCI devices Picasso currently declares the region between TOM and IO_APIC_ADDR. This region includes MMCONF. We don't want to map any PCI BARs in this region. TEST=Boot majolica and check logs pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff] pci_bus 0000:00: root bus resource [bus 00-3f] Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ff02012795e2166e3a4197071b1136727089318 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50893 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-22	soc/amd/cezanne/acpi/soc.asl: Add platform.asl	Raul E Rangel
	Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I01adba010bfad1bb4fdf20a8d0ab22aeeebeb10a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-22	soc/amd/cezanne/acpi: Add MMIO devices	Raul E Rangel
	The devices were copied from picasso with the following modifications: * UART{2,3} were deleted * I2C{0,1} were added * eMMC was removed since it hasn't been validated Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-13	soc/amd/cezanne/acpi: Add plain soc.asl	Raul E Rangel
	Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I227cdb7cb4848d1d26f6d7fa13ac2cc1aea08d1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>