coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-01-29	soc/amd/cezanne: add empty ramstage FCH support	Felix Held
2021-01-27	soc/amd/cezanne: Add UCODE firmware to CBFS	Zheng Bao
2021-01-27	soc/amd: Throw an error if FWM_POSITION_INDEX is empty	Zheng Bao
2021-01-24	soc,vendorcode/amd/cezanne: add basic FSP integration	Felix Held
2021-01-24	soc/amd/cezanne: Add PSP integration for cezanne	Zheng Bao
2021-01-21	soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16	Felix Held
2021-01-14	soc/amd/cezanne: add AOAC support	Felix Held
2021-01-14	soc/amd/cezanne: add console UART support	Felix Held
2020-12-18	soc/amd/cezanne: add GPIO support	Felix Held
2020-12-13	soc/amd/cezanne: add caching setup in bootblock	Felix Held
2020-12-11	soc/amd/cezanne: add 0xcf9 reset	Felix Held
2020-12-11	soc/amd/piasso,cezanne: add warning about using all-y in Makefile.inc	Felix Held
2020-12-09	soc/amd/cezanne: add basic early FCH initialization to bootblock	Felix Held
2020-12-06	soc/amd/cezanne: add config.c and minimal chip.h	Felix Held
2020-12-06	soc/amd/cezanne: use common TSC and monotonic timer code	Felix Held
2020-12-05	soc/amd/cezanne: add skeleton for new SoC	Felix Held