| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-11-27 | security/intel/txt: Issue a global reset when TXT_RESET bit is set | Michał Żygowski |
| 2021-11-27 | security/intel/txt: Correct reporting of chipset production fuse state | Michał Żygowski |
| 2021-06-21 | security/intel/txt: Split off microcode error types string printing | Arthur Heymans |
| 2021-05-20 | security/intel/txt: Add weak function to skip TXT lockdown | Arthur Heymans |
| 2020-11-04 | haswell: Add Intel TXT support in romstage | Angel Pons |
| 2020-07-31 | security/intel/txt: Add Intel TXT support | Philipp Deppenwiese |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |