coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-04-24	{drivers,northbridge,security}: Remove unused <cpu/x86/lapic.h>	Elyes HAOUAS
2021-11-27	security/intel/txt: Issue a global reset when TXT_RESET bit is set	Michał Żygowski
2021-11-27	security/intel/txt: Use set_global_reset in txt_reset_platform if possible	Michał Żygowski
2021-11-27	security/intel/txt: Implement GETSEC PARAMETER dumping	Michał Żygowski
2021-11-27	security/intel/txt: Remove unused region device	Michał Żygowski
2021-11-27	security/intel/txt: Correct reporting of chipset production fuse state	Michał Żygowski
2021-10-05	src/mainboard to src/security: Fix spelling errors	Martin Roth
2021-07-14	include/cpu/x86/msr: introduce IA32_MC_*(x) macros	Felix Held
2021-07-12	security/intel/txt: use mca_get_bank_count()	Felix Held
2021-07-12	security/intel/txt: add missing cpu/x86/msr.h include	Felix Held
2021-03-17	cbfs: Replace more instances of cbfs_boot_locate() with newer APIs	Julius Werner
2020-11-04	haswell: Add Intel TXT support in romstage	Angel Pons
2020-10-22	sec/intel/txt: Extract BIOS ACM loading into a function	Angel Pons
2020-10-22	sec/intel/txt/common.c: Only log ACM error on failure	Angel Pons
2020-10-17	sec/intel/txt: Bail if var MTRRs cannot snugly cache the BIOS ACM	Angel Pons
2020-10-12	security/intel/txt: Clean up includes	Angel Pons
2020-08-07	security/intel/txt: Allow using CF9 reset, too	Angel Pons
2020-08-06	security/intel/txt: Avoid shifting by a negative value	John Zhao
2020-07-31	security/intel/txt: Add Intel TXT support	Philipp Deppenwiese