index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
gitea
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
northbridge
Age
Commit message (
Expand
)
Author
2016-08-01
Add newlines at the end of all coreboot files
Martin Roth
2016-07-31
src/northbridge: Capitalize CPU, RAM and ROM
Elyes HAOUAS
2016-07-28
bootmode: Get rid of CONFIG_BOOTMODE_STRAPS
Furquan Shaikh
2016-07-27
nb/intel/x4x: Fix CAS latency detection and max memory detection
Damien Zammit
2016-07-26
intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
Kyösti Mälkki
2016-07-19
nb/intel/x4x: Fix CAS latency detection
Damien Zammit
2016-07-15
intel/x4x: Do not use scratchpad register for ACPI S3
Kyösti Mälkki
2016-07-15
intel/pineview: Do not use scratchpad register for ACPI S3
Kyösti Mälkki
2016-07-15
AGESA: Use common romstage ram stack
Kyösti Mälkki
2016-07-14
nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declaration
Jonathan Neuschäfer
2016-07-09
nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM
Damien Zammit
2016-07-07
intel/sandybridge: read correct leaf for cpu family
Ryan Salsamendi
2016-06-26
intel/i945: Use common ACPI S3 recovery
Kyösti Mälkki
2016-06-23
intel/sandybridge: Fix builds with System Agent blob
Kyösti Mälkki
2016-06-22
Ignore RAMTOP for MTRRs
Kyösti Mälkki
2016-06-22
intel/model_206ax: Prepare for dynamic CONFIG_RAMTOP
Kyösti Mälkki
2016-06-20
nb/intel/sandybridge/raminit: Use supported CAS
Patrick Rudolph
2016-06-20
nb/intel/sandybridge/raminit: Do code cleanup
Patrick Rudolph
2016-06-20
nb/intel/sandybridge/raminit: Do code cleanup
Patrick Rudolph
2016-06-20
nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devices
Patrick Rudolph
2016-06-17
intel/model_206ax: Move platform specific defines
Kyösti Mälkki
2016-06-17
Move definitions of HIGH_MEMORY_SAVE
Kyösti Mälkki
2016-06-12
nb/intel/raminit (native): Read PCI mmio size from devicetree
Patrick Rudolph
2016-06-12
nb/intel: Factor out common MRC code
Patrick Rudolph
2016-06-04
nb/intel/x4x: Fix unpopulated value
Damien Zammit
2016-06-04
gm45: enable setting all vram sizes from cmos
Arthur Heymans
2016-06-04
AGESA: Fix invalid use of CFG_ declarations
Kyösti Mälkki
2016-05-31
nb/intel/x4x: Add DMI/EP init
Damien Zammit
2016-05-31
Fix leaking CONFIG_VGA=y
Kyösti Mälkki
2016-05-17
intel/sch: Merge northbridge and southbridge in src/soc
Stefan Reinauer
2016-05-09
nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structure
Timothy Pearson
2016-05-09
nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15h
Timothy Pearson
2016-05-08
intel/pineview: Don't try to store 34 bits in 32
Stefan Reinauer
2016-05-06
amd/gx2 + amd/lx: Fix shift overflow issue
Stefan Reinauer
2016-05-05
rdc/r8610: Move to src/soc
Stefan Reinauer
2016-05-05
dmp/vortex86ex: Merge northbridge and southbridge into soc
Stefan Reinauer
2016-05-04
nb/intel/sandybridge/raminit: support calling dram_freq multiple times
Patrick Rudolph
2016-05-04
nb/intel/sandybridge/raminit: add additional fallbacks
Patrick Rudolph
2016-05-04
nb/intel/gm45: Fix native text mode initialization
Nick High
2016-05-02
nb/amd/mct_ddr3: Only initialize ECC bits once
Timothy Pearson
2016-05-01
nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15h
Timothy Pearson
2016-05-01
nb/amd/mct_ddr3: Stop receiver enable cycle training after window found
Timothy Pearson
2016-05-01
nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0
Timothy Pearson
2016-05-01
nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4
Timothy Pearson
2016-05-01
nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h
Timothy Pearson
2016-04-29
nb/intel/sandybridge/raminit: fix regression "always use mrccache"
Patrick Rudolph
2016-04-28
nb/amd/mct_ddr3: Restart system on training failure instead of using die()
Timothy Pearson
2016-04-26
nb/amd/mct_ddr3: Report correct DIMM in MRS setup routines
Timothy Pearson
2016-04-26
nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setup
Timothy Pearson
2016-04-25
nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change
Timothy Pearson
2016-04-22
Revert "nb/amd/mct_ddr3: Disable MCE framework during DRAM training"
Timothy Pearson
2016-04-22
nb/amd/mct_ddr3: Enhance debugging around MEMCLK frequency change
Timothy Pearson
2016-04-22
nb/amd/mct_ddr3: Fix RDIMM training on certain DIMMs
Timothy Pearson
2016-04-22
nb/amd/mct_ddr3: Run fence training on each node after memory clock change
Timothy Pearson
2016-04-20
AMD CIMX: Drop unused code
Kyösti Mälkki
2016-04-19
kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme
Stefan Reinauer
2016-04-16
northbridge/amd/{lx,gx2}: remove immediate accesses of 0
Patrick Georgi
2016-04-13
amd/agesa/family12/dimmSpd.c: Indent (tab) fix
Edward O'Callaghan
2016-04-11
and/nb/mct_ddr3: Pack all structures passed to ramstage and set alignment
Timothy Pearson
2016-04-11
nb/amd/amdfam10: Write MCT variables to flash after PCI configuration
Timothy Pearson
2016-04-10
nb/intel/sandybridge/raminit: always use mrccache
Patrick Rudolph
2016-04-08
Revert "nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed"
Timothy Pearson
2016-04-08
nb/amd/mct_ddr3: Reenable sync flood after ECC init
Timothy Pearson
2016-04-08
nb/amd/mct_ddr3: Add MCE reporting logic
Timothy Pearson
2016-04-08
nb/amd/amdfam10: Only flag machine check exception if valid bit is set
Timothy Pearson
2016-04-08
nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform level
Timothy Pearson
2016-04-05
nb/intel/sandybridge/raminit: die in toplevel function
Patrick Rudolph
2016-04-05
nb/intel/sandybridge/raminit: prepare raminit for fallback
Patrick Rudolph
2016-04-01
nb/amd/mct_ddr3: Fix revision mask for DR processors
Timothy Pearson
2016-03-31
nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
Timothy Pearson
2016-03-31
nb/amd/mct_ddr3: Clear early MCEs and report DRAM MCEs
Timothy Pearson
2016-03-31
nb/amd/mct_ddr3: Disable MCE framework during DRAM training
Timothy Pearson
2016-03-30
nb/amd/mct_ddr3: Enable DIMM parity when RDIMMs installed
Timothy Pearson
2016-03-30
northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)
Damien Zammit
2016-03-30
nb/intel/sandybridge/raminit: move ram training into seperate function
Patrick Rudolph
2016-03-29
nb/intel/sandybridge/raminit: move dimm_info into ramctr_timing
Patrick Rudolph
2016-03-28
nb/amd/mct_ddr3: Use standard C function calls in mct_ResetDataStruct_D()
Timothy Pearson
2016-03-26
nb/amd/amdmct: Select max_lanes based on ECC presence or absence
Damien Zammit
2016-03-24
nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained values
Timothy Pearson
2016-03-23
nb/amd/mct_ddr3: Remove spurious Addl_Index variable in dqsTrainMaxRdLatency_...
Timothy Pearson
2016-03-21
nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain set
Timothy Pearson
2016-03-16
cpu/x86/mtrr: move cache_ramstage() to its only user
Aaron Durbin
2016-03-13
nb/amd/mct_ddr3: Use correct initial UI setting during DRAM training
Timothy Pearson
2016-03-13
northbridge/intel/i3100: Unify UDELAY selection
Stefan Reinauer
2016-03-13
northbridge/intel/i82810: Unify UDELAY selection
Stefan Reinauer
2016-03-12
northbridge/intel/i82830: Unify UDELAY selection
Stefan Reinauer
2016-03-12
nb/amd/mct_ddr3: Consolidate duplicated code
Timothy Pearson
2016-03-11
northbridge/intel: move mrccache.c of sandybridge + haswell to common
Alexander Couzens
2016-03-11
northbridge/intel: move mrc_cache definition into a common header
Alexander Couzens
2016-03-11
nortbridge/sandybridge/mrccache: parse the return code of flash->write
Alexander Couzens
2016-03-11
nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Consolidate calls to MCT minimum clock setting fetch
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Require minumum training quality for both read and write
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
Timothy Pearson
2016-03-11
nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop
Timothy Pearson
2016-03-11
northbridge/i945/gma: Re-enable NVRAM tft_brightness
Alexander Couzens
2016-03-10
northbridge/intel/i440bx: Unify UDELAY selection
Stefan Reinauer
2016-03-09
northbridge/intel/gm45: Use TSC for ramstage timer per default
Stefan Reinauer
2016-03-05
sandybridge/gma_lvds: support both Sandy&Ivy on one board
Iru Cai
[prev]
[next]