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2016-09-21northbridge/amd: Improve code formattingElyes HAOUAS
Change-Id: I80a2753f22d5211c8be4e17e2338402286a2cadc Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/amd/amdfam10: Improve code formattingElyes HAOUAS
Change-Id: I86a252598666af635281eaa467020acb53d71c77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/via: Add space around operatorsElyes HAOUAS
Change-Id: I87f8978b8ec6ddc11dd66a77cbb630e057f9831b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16623 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-20northbridge/intel/e7505/debug.c: Improve code formattingElyes HAOUAS
Change-Id: I63f58d95fa01b1f73f3620a5d13f21ef62e2404c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/i3100: Add space around operatorsElyes HAOUAS
Change-Id: I5ff894f23dc2a2c59bc5e5d1de4287a6b9c9922c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16625 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/i945: Add space around operatorsElyes HAOUAS
Change-Id: I24505af163544a03e3eab72c24f25fcdc4b1b16c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16624 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/amd/agesa: Improve code formattingElyes HAOUAS
Change-Id: If700dc5fa9ae33649993557f71db0fe1eb76204b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/e7505: Improve code formattingElyes HAOUAS
Change-Id: I964512c0e913f7443f3dea859b01358645cfd8a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16632 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/i82830: Add space around operatorsElyes HAOUAS
Change-Id: Ic4e287209cc45fae574e7af9d45b8a0e648ef686 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/haswell: Add space around operatorsElyes HAOUAS
Change-Id: I8fa1e39bfd950475e3b55d6debcbfd92615aa379 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16628 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/e7501: Add space around operatorsElyes HAOUAS
Change-Id: I53aa17076135e55665f2f7c6ede217388fc50cca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16633 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/fsp_rangeley: Add space around operatorsElyes HAOUAS
Change-Id: Ia60729db83333c1159862cf604de321e3af8dcb1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16631 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/fsp_sandybridge: Add space around operatorsElyes HAOUAS
Change-Id: I1b5cdfaf39be639a7ef71e66e91284fa186fbb86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16630 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/gm45: Add space around operatorsElyes HAOUAS
Change-Id: I3781c36a3f354bfd54d20488b95d4f2307c3bce2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16629 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-19gm45/gma.c: use correct id string for fake VBTArthur Heymans
The correct id string for gm45 is "$VBT CANTIGA ". This can be found in the gm45 option rom: "strings vbios.bin | grep VBT". Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16551 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-19nb/gm45/gma.c: enable VESA framebuffer mode on VGA outputArthur Heymans
This implements "Keep VESA framebuffer" behavior on VGA output of gm45. This patch reuses Linux code to compute vga divisors. Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16338 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-19gm45/gma.c: use screen on vga connector if connectedArthur Heymans
The intel x4x and gm45 have very similar integrated graphic devices. Currently the x4x native graphic init enables VGA, while gm45 can output on LVDS. This patch reuses the x4x graphic initialisation code to enable output on VGA in gm45 in a way that the behavior is similar to vbios: If no VGA display is connected the internal LVDS screen is used. If an external screen is detected on the VGA port it will be used instead. Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16295 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-15northbridge/intel/nehalem/gma.c: Improve code formattingElyes HAOUAS
Change-Id: Ie7ee547ab34441f93433936334e9881dd7cc0371 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16599 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15northbridge/amd/amdk8/raminit_f_dqs.c: Improve code formattingElyes HAOUAS
Change-Id: Ib1f9926ced1fd382c782f5098eb1ad98330cf655 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16600 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15northbridge/amd/amdk8/coherent_ht.c: Improve code formattingElyes HAOUAS
Change-Id: I296254d61fdc5c120e1e2abcbecb4677f3216d26 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16598 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13i945.h: fix #include pathAntonello Dettori
Fix the #include path. Change-Id: Ifefb2faef6e4fc87152acb21c37dd87e7c14645c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16294 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/intel/nehalem: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/nehalem. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I6da4e0a9ef21b3285f4a369c8ddfbdb32a7a3801 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16406 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/intel/gm45: transation away from device_tFurquan Shaikh
Replace the use of the old device_t definition inside northbridge/intel/gm45. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16402 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/amd/amdht: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/amdht. Change-Id: I7dfb8f001504c691aeddf1bfbc3be05cc7d31ce4 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16468 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/amd/amdk8: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/amdk8. Change-Id: I5209dd309f0685f83d8a468c50309d5fda77973a Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16467 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/amd/amdfam10: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/amd/amdfam10. Change-Id: I5037feb31c51d06ccc672b0771d5d6e8c0dac949 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16466 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12src/northbridge: Improve code formattingElyes HAOUAS
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16414 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12cpu/x86: Move fls() and fms() to mtrr.hRizwan Qureshi
Move the funtion to find most significant bit set(fms) and function to find least significant bit set(fls) to a common place. And remove the duplicates. Change-Id: Ia821038b622d93e7f719c18e5ee3e8112de66a53 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16525 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-10northbridge/intel/x4x: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/x4x. Change-Id: I65cd02eacf57cb41ded434582ca6e9d9f655e6ea Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16472 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10northbridge/intel/i5000: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/i5000. Change-Id: Ic049d882ef22f117ee52ba497351f548e2355193 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16471 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10northbridge/intel/e7505: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/e7505. Change-Id: Ie819f380ec06667e11bcff3e9e993126a86b2c89 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16469 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09northbridge/intel/fsp_rangeley: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/fsp_rangeley. Change-Id: I4c1e6af64fe70211db2fafdba9f39182dfea66fc Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16470 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09nb/intel/gm45: Fix DMAR table - IOMMU advertisement for ME interfacesDamien Zammit
Previously the ME PCI interface (HECI) was being reported as present in the DMAR ACPI table even when ME firmware was missing or the PCI device was hidden and HECI would be unresponsive. Now we check via the PCI config space itself to verify if the HECI is present or not. Note that this test could fail if ME firmware is present but HECI is disabled in devicetree, because it would not advertise that the HECI exists even though there is a running ME. Perhaps this behaviour is desirable because in this case you won't see the HECI in the lspci tree anyway. Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16330 Tested-by: build bot (Jenkins) Reviewed-by: Swift Geek <swiftgeek@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07nb/intel/x4x: Correct typos in interrupt routing for PEGDamien Zammit
Device 1 on secondary bus instead of device 0 was being routed. Change-Id: I4207938038acf7ff941afd692e90a690d2426a05 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16515 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07nb/intel/x4x: Turn on PEG graphics in device enableDamien Zammit
Change-Id: I389c4630362af1c1bf6d281c9d2b7fc81bea2d5d Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16495 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-07nb/intel/x4x: Increase MMIO PCI space to 2GiBDamien Zammit
This is necessary for PCI express graphics card add-ons, otherwise the pci allocator cannot fit the mmio for the add on card into the space it has available and the OS turns off the card. Old value was 1GiB. Change-Id: I606994501b15e636fe209d1ed4b3d3f73b42bf5c Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07nb/intel/x4x: Fix DMI initDamien Zammit
No more hang on DMI init when wait for DMI is re-enabled. Previously the virtual channel arbitration table was not being set up in the south/north bridges causing invalid DMI state. This has been tested on GA-G41M-ES2L with patches following. An NVIDIA GT218 card was detected by the OS and displayed using the nouveau driver with no blobs. Change-Id: I35e03c40f5f7aa4915afd5d26db7ab053abcf0cd Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16491 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-07gm45/gma.c: clean up some registersArthur Heymans
According to "G45: Volume 3: Display Register Intel ® 965G Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller" some registries are set incorrectly in gm45/gma.c. Some values are changed after comparing them with the values the i915 linux kernel (3.13 was used) module sets while modesetting. The values were obtained using 'intel_reg' from intel-gpu-tools, during a normal boot and with 'nomodeset' as a kernel argument. Some registers that don't exist on gm45 are set in gma.c, which is probably the result of copying code from a more recent intel northbridge. The result is that that gm45 laptops with wxga displays still work as before. gm45 laptops with wxga+ or higher resolution now just work, where previously a black screen was shown. TEST: build with native graphic init and flash on a gm45 target, like lenovo x200. Change-Id: If66b60c7189997c558270f9e474851fe7e2219f1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16217 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07northbridge/amd/lx: remove unused function declarationAntonello Dettori
Remove an unusued function declaration that caused problems while compiling the target. Change-Id: Idfd73693e9b0e1777cafa4706113fde394e95795 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16435 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04northbridge/intel/i945: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/i945. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I041c150a7b50261e26955ad9287ef05b9a06e412 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16371 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-04northbridge/intel/sandybridge: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/sandybridge. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I35cc76ec7b6baa216666d06f6f325f43ac69067e Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16409 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31northbridge/intel: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I53208ce5db06d2c65f954e6d59222924ab87722e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16304 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31northbridge/amd: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ic85f725bbdf72fbac5a4d9482c61343c5eb35e25 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16305 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31northbridge/via: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: Ic644cf6792a5d360527e48e04c74ae92be0d1d4f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16284 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31i945: Enable changing VRAM sizeArthur Heymans
On i945 the vram size is the default 8mb. It is also possible to set it 1mb or 0mb hardcoding the GGC register in early_init.c The intel documentation on i945, "Mobile Intel® 945 Express Chipset Family datasheet june 2008" only documents those three options. They are set using 3 bits. The documententation also makes mention of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it. The other non documented (straight forward) bit combinations allow to change the VRAM size to those other states. What this patch does is: - add those undocumented registers with their respective vram size to the i945 NB code; - make this a cmos option on targets that have this northbridge. TEST: build, flash to target, set cmos as desired and boot linux. On Debian it can be found using "dmesg | grep stolen". NOTE: dmesg message about reserved vram are quite different depending on linux version Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23src/northbridge: Remove unnecessary whitespace before "\n" and "\t"Elyes HAOUAS
Change-Id: I6a533667c7c8ff5ec6ab9d4e1cfc51e993a90084 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16280 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-09x4x: make preallocated IGD memory a cmos optionArthur Heymans
This allows to set the preallocated memory for the IGD on x4x using a cmos option. If no cmos option is found a default value of 64M is used. TESTED most options on ga-g41m-es2l with 2G dimm in one slot and 2x2G. 352M also works in contrast with gm45 where it is known to cause issues with certain ram combinations. Change-Id: I9051d080be82f6dfab37d353252e29b2ed1fca7f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15492 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-09x4x: add non documented vram sizesArthur Heymans
The Intel documtentation, "Intel ® 4 Series Chipset Family" mentions the possibility of 1, 4, 8 and 16M of preallocated memory for the IGD, but does not document this. This allows to set those undocumented values. TESTED on ga-g41m-es2l with 2G dimm in one slot and 2x2G. Change-Id: I92beb8d78907d4514a5aaf69248dd607dcf227c0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15491 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-02amd/amdfam10: eliminate dead codePatrick Georgi
if (gart) { foo = gart?a:b; } never evaluates to foo=b. Change-Id: Ibc7376687374065585b125a670dea5fe46bda97a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1347365 Reviewed-on: https://review.coreboot.org/16008 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31src/northbridge: Capitalize CPU, RAM and ROMElyes HAOUAS
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27nb/intel/x4x: Fix CAS latency detection and max memory detectionDamien Zammit
Now hardcode maximum memory frequency capability to 800MHz, as all chipsets in x4x family support PC2-6400 according to the datasheet. CAS latency detection also relies on this, and has been cleaned up. Ram initialization does not work with FSB 1333MHz / DDR2 800MHz combination, so disable this combination for now, and reduce to 667MHz instead. Still don't know why this is the case, but FSB1333/667 works. These changes should now allow existing configurations to continue working, while providing support for previously unworking configurations, due to previous buggy CAS latency detection code. TESTED: on GA-G41M-ES2L CPU: E5200 @ 2.50GHz (FSB 800MHz) 2x 1GB 667MHz hynix worked @ 667 1x 2GB 800Mhz ARAM worked @ 800 1x 1GB 667Mhz StarRam worked @ 667 2x 2GB 800Mhz (generic) worked @ 800 Change-Id: I1ddd7827ee6fe3d4162ba0546f738a8f9decdf93 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15818 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-26intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZEKyösti Mälkki
Match the definition and use of these variable with haswell, such that DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE. Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15761 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19nb/intel/x4x: Fix CAS latency detectionDamien Zammit
Fix and use the failsafe CAS detection logic rather than recalulating the values from raw SPDs. Tested on GA-G41M-ES2L with 2x2GB DDR2-800 DIMMs (which worked before and still work) Change-Id: I6af0f1705d099f7bcbff8c9baa94a68dae689e01 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15726 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2016-07-15intel/x4x: Do not use scratchpad register for ACPI S3Kyösti Mälkki
If S3 support was implemented for this platform later on, use romstage handoff structure instead. Change-Id: I03c1e07a7fcc17c27203d0c4e32e3958f2ba5273 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15716 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15intel/pineview: Do not use scratchpad register for ACPI S3Kyösti Mälkki
If S3 support was implemented for this platform later on, use romstage handoff structure instead. Change-Id: Ib0cf3ad41753baee26354c5ed19294048e7fb533 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15715 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15AGESA: Use common romstage ram stackKyösti Mälkki
Change-Id: Ie120360fa79aa0f6f6d82606838404bb0b0d9681 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declarationJonathan Neuschäfer
Change-Id: I7c3973ff325f11a86728e8660c70839776981aa5 Reported-by: GCC 6.1.0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-09nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAMDamien Zammit
Previously, any 800MHz DIMMs were being slowed to 667MHz for no reason other than there was a bug in the maximum frequency detection code for the MCH. Change-Id: Id6c6c88c4a40631f6caf52f536a939a43cb3faf1 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15257 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-07intel/sandybridge: read correct leaf for cpu familyRyan Salsamendi
Reading cpuid leaf 0 is incorrect for testing cpu family. Use leaf 1 instead. See Intel SDM 2a Table 3-17. Change-Id: Ib2c95cdd1fb93db06a08ecd7266f6b88700caf83 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/15346 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-06-26intel/i945: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: I6f0cdc80870fddeaada3191e493bd85fdefee07f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15245 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-23intel/sandybridge: Fix builds with System Agent blobKyösti Mälkki
Broken with commit: 5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS Available sandybridge/systemagent-r6.bin has MMCONF hard-coded at some places and samsung/lumpy fails at boot here: CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 2fc94 System Agent: Starting up... System Agent: Initializing These are the last lines as captured over USB debug. Change-Id: I441847f0e71a5e1be9c8ef6a04a81eb7bdd8a6d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15328 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22intel/model_206ax: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: Ib3250677ee926deaa957c83aca7479eb0159358c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15231 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20nb/intel/sandybridge/raminit: Use supported CASPatrick Rudolph
Instead of programming unsupported CAS use the highest supported value. Start at DDR3 maximum of CAS 18T. Increase error message verbosity level. Useful for overclocking. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Allows to run a DDR3-1600 DIMM at 933Mhz. Change-Id: I2e8aadd541f06fa032ad7095c9a2d5e3bb7613f3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15217 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
Calculate the value from current DDR frequency. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15184 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
Simplify calculation of value. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Change-Id: I3ecd12c431b46a8d2218f33d7eb3e10de3bcd61d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15181 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devicesPatrick Rudolph
Set max_mem_clock_mhz in devicetree to 933Mhz. Allows to run the memory at up to DDR3-1866. The same frequency was allowed within the first vendor bios, but Lenovo than decided to limit it to DDR3-1333. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). The RAM is now running at DDR3-1600 instead of DDR3-1333. This gives about 4% performance increase in glmark2 using the Intel GPU. Change-Id: If15be497402d84a2778f0434b6381a64eda832d6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15158 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
Change-Id: I3c517fc55dd333b1a457324f1d69aeb6f70acec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15197 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
This is more of ACPI S3 resume and x86 definition than CBMEM. Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15190 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-12nb/intel/raminit (native): Read PCI mmio size from devicetreePatrick Rudolph
Instead of hardcoding the PCI mmio size read it from devicetree. Set a default value of 2048 MiB and 1024MiB for laptops without discrete graphics. Tested on Sandybridge Lenovo T520. Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12nb/intel: Factor out common MRC codePatrick Rudolph
Remove code duplication and use the common function store_current_mrc_cache instead. No functionality is changed. Tested on Sandybridge Lenovo T520. Change-Id: I4aa5463f1b1d5e1afbe44b4bfc659524d86204db Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15074 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-04nb/intel/x4x: Fix unpopulated valueDamien Zammit
Previously, 0x0 was the value being used for an unpopulated dimm on spd[62], however some DDR2 dimms have 0x0 as a valid value. Now use 0xff which is an unused value even on DDR2/DDR3. Change-Id: I55a91a6c3fe3733a7bb2abc45ca352c955c07c99 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15058 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04gm45: enable setting all vram sizes from cmosArthur Heymans
Setting the size of the preallocated memory for the igd is done using a cmos parameter, gfx_uma_size. This was limited to a subset of all available sizes, that were already implemented elsewhere in the northbridge code. What this does is change the cmos parameter to 4 bits instead of 3 bits to accomodate all vram sizes. It also adds a sane default of 32mb that already was in place. The northbridge code that reads this cmos parameter is also changed for this new cmos settings. 352M is disabled since it causes issues on systems with 4GB or more ram. TEST: Build, flash target. Clear cmos by corrupting the checksum (nvramtool -c something). Set a desired value in gfx_uma_size using nvramtool. "dmesg | grep stolen" to see what is actually allocated. Change-Id: Ia6479d03f1abe6d0c94bd7264365505e8f8eaeec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14900 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-06-04AGESA: Fix invalid use of CFG_ declarationsKyösti Mälkki
The declarations of CFG_ evaluate to correct values only when included after the definitions of BLDCFG_ in buildOpts.c. So we never have CFG_PLAT_NUM_IO_APICS defined here. Change-Id: I94b3dee5a3207b37921eb24a0bcd73b5a217b2d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14887 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31nb/intel/x4x: Add DMI/EP initDamien Zammit
The values were obtained from vendor bios at runtime. I am not 100% sure of the sequence required to initiate them, but guessed from the gm45 code. There may be some status bytes needed to be polled during the sequence that is missing, but as I don't have bios writer's datasheet it's very hard for me to know. Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/14925 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31Fix leaking CONFIG_VGA=yKyösti Mälkki
Items under DEVICE_SPECIFIC_OPTIONS got selected without the driver being selected. Change-Id: I1797fa6175620a9291873559a6308eaea85a090e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14823 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-17intel/sch: Merge northbridge and southbridge in src/socStefan Reinauer
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-05-09nb/amd/mct_ddr3: Report correct DIMM size in SMBIOS structureTimothy Pearson
The existing DIMM size calculation for DDR3 was incorrect. Use the recommended calculation from the DDR3 SPD specification. Change-Id: Id6a39e2b38b5d9f483341ebef8f2960ae52bda6c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14739 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15hTimothy Pearson
While some stubs existed before this patch to handle non-ECC memory initialization, there were a number of ECC detect unaware sections of code. Add ECC support detection to those sections. Change-Id: I56dad8a0f6833b2f42796212afb9777e9cc73d6d Tested-On: ASUS KGPE-D16 Tested-With: 1x Opteron 6262 Tested-With: 1x SuperTalent 4G non-ECC DIMM in slot A2 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14737 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Damien Zammit <damien@zamaudio.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-08intel/pineview: Don't try to store 34 bits in 32Stefan Reinauer
Mask out the bit that doesn't fit in 32bits, so gcc 6.1 is happy Change-Id: I13e2b41742206b8d86b90314b80cc324c00ae637 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14639 Reviewed-by: Damien Zammit <damien@zamaudio.com> Tested-by: build bot (Jenkins)
2016-05-06amd/gx2 + amd/lx: Fix shift overflow issueStefan Reinauer
gcc 6.1 complains that SMM_OFFSET << 8 is larger than the register it is assigned to (rightly so): src/northbridge/amd/gx2/northbridgeinit.c:196:23: error: result of '1077936128 << 8' requires 40 bits to represent, but 'int' only has 32 bits [-Werror=shift-overflow=] msr.lo = (SMM_OFFSET << 8) & 0xfff00000; ^~ Change-Id: Ib0d669268202d222574abee335a6a65c8a255cc7 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14617 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-05rdc/r8610: Move to src/socStefan Reinauer
Change-Id: I99e5d7f3b46c90ca863ddf6c186b5447d0c8e6f2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14607 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-05-05dmp/vortex86ex: Merge northbridge and southbridge into socStefan Reinauer
Change-Id: I16c04452d2d6c3205aea29fe8aa8fad8fc485a46 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14600 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-05-04nb/intel/sandybridge/raminit: support calling dram_freq multiple timesPatrick Rudolph
The PLL will never lock if the requested frequency is already set. As the fallback may request the same frequency again exit early to prevent a hang. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I625b2956346d8c50cca84def6190c076bf99dbec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14174 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04nb/intel/sandybridge/raminit: add additional fallbacksPatrick Rudolph
Add the following fallbacks: * Try decreasing clock frequency. In case of DDR1600 the next possible value of DDR1333 is being used. * Try decreasing clock frequency. In case of DDR1333 the next possible value of DDR1066 is being used. * Disable failing channel. The system may be able to boot with a single channel enabled. The fallbacks are untested. Change-Id: I3be7034ad25312b3ebf47a54f335a3893f8d7cc1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14173 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04nb/intel/gm45: Fix native text mode initializationNick High
The LVDS port is configured to accept data from pipe A, but the panel fitter and VGA were attached to pipe B. Changes to VGACNTRL: - select pipe A instead of pipe B. - disable VGA centering to fix jitter. TEST=Build and run on Thinkpad X200 in both text and framebuffer modes. Change-Id: I2356f264580d8b021952c217de3477291d866f98 Signed-off-by: Nick High <nhigh@openmailbox.org> Reviewed-on: https://review.coreboot.org/14524 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-05-02nb/amd/mct_ddr3: Only initialize ECC bits onceTimothy Pearson
The ECC check bits of all ECC DIMMS were inadvertently initialized twice in the same routine, significantly delaying startup. Part of this was related to an obsolete MCA workaround that has been fixed through multiple commits, therefore the workaround is no longer needed. Only initialize the ECC check bits once. Change-Id: I90ac1147d9b006794d29b866a9cb5b7ead8f01e7 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14503 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-05-01nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15hTimothy Pearson
Change-Id: Idb948acd1a508379f600fbd2fd40fb26b7571d7c Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14545 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01nb/amd/mct_ddr3: Stop receiver enable cycle training after window foundTimothy Pearson
During receiver enable cycle training on Family 15h the entire range of possible delays is searched, even though the single passing window is often found nearly immediately. Skip the remainder of the delay range after the passing window has been located. Change-Id: If98217fa8e7de77366762d3c7bb01049a1dc080f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14544 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0Timothy Pearson
During DQS receiver enable cycle training on Family 15h platforms the read data timing registers were inadvertently set to zero on every lane training attempt. Ensure that the read data timing registers are correctly set after each lane is trained in receiver enable cycle training. This allows more than one RDIMM to function on a given DCT channel. Change-Id: I87d732f0383e9785a73b57e6f48855f3e872f1f9 Tested-On: ASUS KGPE-D16 Tested-With: 1x Opteron 6262HE Tested-With: 4x Crucial 36KSF1G72PZ-1G6M1 (slots A2 / A1 / B2 / B1) Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14543 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4Timothy Pearson
Change-Id: I1f5b024606093dc81de3f3d69b7a43e20141b709 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14542 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-01nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15hTimothy Pearson
The existing Family 15h receiver enable training code stored temporary delay values in the wrong variables, leading to the requisite averaging of delays across nibbles not being applied. This in turn made x4 DIMMs less stable than they should have been. Store temporary nibble delay values in a dedicated array. Change-Id: Ic5da898af7d689db4110211f89b886ccdbb5f78f Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14541 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-29nb/intel/sandybridge/raminit: fix regression "always use mrccache"Patrick Rudolph
Fix regression introduced by: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Don't run channel_test on S3 resume as it overrides memory that might be in use. Fixes MCE events reported by the GNU/Linux kernel that low memory has been modified. Reset on failed s3 resume. Change-Id: Ibadea286619c7906225f86a93aaa0b4caf26cabe Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-28nb/amd/mct_ddr3: Restart system on training failure instead of using die()Timothy Pearson
DIMM training can sporadically fail due to external influences or various errata. In these cases, restarting to retry training is a more appropriate response than halting the system and requiring manual intervention. Change-Id: Id49f7419f56e0640a84448cc06ecbaf62bed145e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14529 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-26nb/amd/mct_ddr3: Report correct DIMM in MRS setup routinesTimothy Pearson
The wrong DIMM number was used in the initial non-target MRS setup routines. This had no functional impact other than to print the wrong DIMM number in the DDR3 verbose debug output. Change-Id: I480118ed00e1786a06e641a56f0fb19cd87f92eb Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14501 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-26nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setupTimothy Pearson
The existing RDIMM RC control word send routines were a hodgepodge of various AGESA chunks with different ways of handling the same task. Unify the control word chip select setup, use precise timing routines on Family 15h, fix a couple of incorrect masks, and add additional debugging statements. It is believed that this patch is cosmetic and does not significantly alter existing functionality. Change-Id: Ie4ec7b6a7be7fce09e89f9eec146cc98b15b6160 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14500 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-25nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK changeTimothy Pearson
When more than one DIMM is installed on a DCT, only the first DIMM delay values are scaled to the new memory clock frequency after a memory clock change during write leveling. Store the previous memory clock of each DIMM during write leveling to ensure that every DIMM has its delay values rescaled. Change-Id: I56e816d3d3256925598219d92783246f5f4ab567 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14479 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 04:35:46 +0000