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2020-12-14nb/intel/ironlake: Add comment about MCH scan chainsAngel Pons
Change-Id: I3e60cfc1fd3352b8b0c7460503179425cc593d36 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-14nb/intel/ironlake: Remove unused constantAngel Pons
Change-Id: I0a32295e72270cde2e9bd2f8f00358b47ffd3e33 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48562 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-13nb/intel/sandybridge: Clean up program_timingsAngel Pons
Clarify the clock, command and control programming sequence. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I1aa4144197dc25dc8d6ef1d23e465280bddd95a3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47770 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-12nb/intel/sandybridge: Clean up stepping logicAngel Pons
Do not combine the host bridge device ID with the CPU stepping because it is confusing. Although Sandy/Ivy Bridge processors incorporate both CPU and northbridge components into the same die, it is best to treat them separately. Plus, this change enables moving CPU stepping macros from northbridge code into the CPU scope, which is done in a follow-up. Change-Id: I27ad609eb53b96987ad5445301b5392055fa4ea1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-12nb/intel/sandybridge: Fix blunder in MR2 shadow codeAngel Pons
Commit 7f1363d9b4 (nb/intel/sandybridge: Program MR2 shadow register) has a bug where the system locks up and power cycles when booting Linux, but is still able to pass memtest86+ with flying colors. The issue will occur when the following conditions are true: - CPU is Ivy Bridge - Memory speed is not greater than 1066 MHz (DDR3-2133 or slower) - System contains dual-rank DIMMs - The second rank of the dual-rank DIMMs is mirrored - All DIMMs support Extended Temperature Range - At least one of the DIMMs does not support Auto Self-Refresh If all of these conditions are met, the final value of the MR2 Shadow registers configures the memory controller to issue a MRS command to update MR2 before entering self-refresh mode, but indicates that rank mirroring is not required (the first rank on a DIMM is never mirrored). Before the memory controller enters self-refresh, it sends MRS commands to all ranks to update MR2, but the missing address and bank mirroring means DRAM chips on mirrored ranks instead clobber MR1 with junk data. With garbage in MR1, the mirrored ranks no longer function properly, which ultimately leads to all hell breaking loose (undefined behavior). The condition is backwards, since only odd ranks can be mirrored. To avoid this problem completely, simply remove the condition. The final register value will still be correct, since the bits are always ORed. Tested on Asus P8Z77-V LX2, fixes booting Linux with dual-rank DIMMs. Change-Id: Iceff741eb85fab0ae846e50af0080e5ff405404c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-07nb/intel/ironlake: Introduce memmap.hAngel Pons
Move all memory map definitions into a separate header. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I1f37ad9cae39041f98871c613b308b5ac5da01b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45379 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
There's no need to wrap these macros with casts. Removing them allows dropping more casts in `early_init.c`. To avoid binary changes the casts are put into the {MCH,DMI,EP}BAR{8,16,32} macros instead where they are needed to reach the right memory locations. Change-Id: Icff7919f7321a08338db2f0a765ebd605fd00ae2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07nb/intel/i945: Introduce memmap.hPatrick Georgi
Inspired by Idca25b2e4bf65abcb and Ib275f9ad8ca9ff move all memory map definitions into a header with a common name. Change-Id: I32a99f70f4d2eb52367c9edfc0aa6d5da2fec03f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-03cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()Julius Werner
This patch introduces two new CBFS API functions which are equivalent to cbfs_map() and cbfs_load(), respectively, with the difference that they always operate on the read-only CBFS region ("COREBOOT" FMAP section). Use it to replace some of the simple cases that needed to use cbfs_locate_file_in_region(). Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39306 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Enable CBFS mcache on most chipsetsJulius Werner
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-25nb/amd: Deduplicate nb_common.hAngel Pons
Save for the IO_APIC2_ADDR definition, they are equivalent. Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47408 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-25device: Drop unused HyperTransport codeAngel Pons
Only two definitions are actually used somewhere, the rest is unused. Change-Id: Iec52d0d47fce6a1ec5455b670824b995a7a34a4c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47407 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-23nb/amd/agesa/family15tn: define macros for GNB and IOMMU devicesMike Banon
Follow the example of newer AMD code for Stoneyridge and Picasso. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-23nb/amd/agesa/family15tn: define macro for internal HDMI audio controllerMike Banon
Following the example of CB:7630 done for family16kb boards (git commit 3ff4f85ccd9fdb7cd4885a10f025b5ab297a445f). Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: Ic48c7475ceadb60f825ca9e3c3427c8a7525a266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22nb/amd/pi: Remove 00660F01 directory & filesMartin Roth
These files are not used by any platform, so remove them. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I75651d2cc53fc5a3cb3233686ad66881d129312d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22cpu/amd/pi: Remove unused cpu code 00660F01Martin Roth
Remove the processor directory and references to the Kconfig symbol. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I403a453362fd76d6ef2a5b75728a362efa4f2491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22nb/intel/sandybridge: Clean up COMPOFST1 logicAngel Pons
This register needs to be updated differently depending on the CPU generation and stepping. Handle this as per reference code. Further, introduce a bitfield for the register to make the code easier to read. Change-Id: I51649cb2fd06c5896f90559f59f25d49a8e6695e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Correct get_COMP2 functionAngel Pons
Values differ between Sandy and Ivy Bridge. Remove the lookup table, since it contains duplicated values and is hard to see which values correspond to which frequencies. New values come from reference code. Change-Id: I3b28568f0053f1b39618e16bdffc24207547d81f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Rename and refactor `discover_timC_write`Angel Pons
This is actually aggressive write training, similar to aggressive read training. Rename it accordingly and refactor it to improve clarity. Enabling IOSAV_n_SPECIAL_COMMAND_ADDR optimizations must only be done for later Ivy Bridge steppings. Therefore, guard the code accordingly. Change-Id: Ia3331b95c265113d94cb5d66c57a97cb77fc3dc9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Only use write Vref if supportedAngel Pons
Only some Ivy Bridge SKUs support write Vref control. Change-Id: I4e606c69c6758d909946da43c3d243e3af8833cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Refine power-down mode logicAngel Pons
When memory is running at fast frequencies, power-down modes can lessen system stability. Check tXP and tXPDLL values and use safer power down modes if their values are high. Do not use APD with DLL-off on mobile: vendor firmware does not use it, and it can influence system stability. Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Lower tPRPDEN to 1Angel Pons
This is the default value, and matches what vendor firmware does. Change-Id: Id0c9758a845d711a87c4b06f89fa0926ae658e02 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Increase tRWDRDD with fast RAMAngel Pons
This has been reported to increase stability, and vendor BIOS also does the same. Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Rename and clean up `discover_edges_write`Angel Pons
This is actually an (incomplete) aggressive read training algorithm. Rename functions and variables accordingly, and tidy up declarations. Tested on Asus P8H61-M PRO, still boots. Change-Id: I8a4900f8e3acffe4e4d75a51a2588ad6b65eb411 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Relocate PREA-ACT-RD sequenceAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie5e243380d940ca89857b230e15091ac01fde928 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Remove spurious writes to IOSAV BW maskAngel Pons
The byte-wise error mask only needs to be set for certain corner cases in read MPR training. Thus, minimize writes to this register. Tested on Asus P8H61-M PRO, still boots. Change-Id: I0bb8d99ad60c4964f896d303878e5982ae1dcdbe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Drop `precharge` functionAngel Pons
This is a copy of `find_predefined_pattern` without any effect. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ieb72066ca25b40b6e60f04e6c4097a0ccc2a56b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Clarify register writeAngel Pons
It is necessary to program this register before doing an I/O reset. Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Encapsulate JEDEC write levelingAngel Pons
Create and rename a few functions to contain the entire JEDEC write leveling algorithm. Not all write training is JEDEC write leveling. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie9c6315340164029e30354723b4103d906633602 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Do not rewrite write leveling sequenceAngel Pons
There's no need to reprogram the exact same sequence over a hundred times. Move it out of the timB loop, and drop the `test_timB` function. Tested on Asus P8H61-M PRO, still boots. Change-Id: I375e325cf8b5369889b9cb059c3675cd00bdbb3f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Make helper for write leveling sequenceAngel Pons
Encapsulate the IOSAV sequence into a helper to help reduce clutter. Tested on Asus P8H61-M PRO, still boots. Change-Id: I58595a5c53fcdc3f29fa55b015a82cbfe85cd6cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Run `read_mpr_training` before write trainingAngel Pons
Reference code does this, so follow suit. Tested on Asus P8H61-M PRO, still boots. Change-Id: I21c5161da55b380dd4b2d574b22a1ef038f55fce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Rename `read_training` functionAngel Pons
Given that it sets the receive enable mode bit in the GDCRTRAININGMOD register, it's clear that this is about receive enable calibration. Remove a potentially-outdated comment. Proper documentation will be written once code refactoring and various improvements are complete. Change-Id: Iaefc8905adf2878bec3b43494dc53530064a9f5d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47576 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD registerAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47572 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use bitfield for GDCRCMDPICODINGAngel Pons
This register's layout makes no sense, so use bitfields for clarity. Tested on Asus P8H61-M PRO, still boots. Change-Id: I61efc7349badc2c3297c9b71535dceecaba509d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Move constants out of for-loopAngel Pons
Most per-channel registers are programmed with the same values. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ifddff3043b68113058859cef08625b90012ca424 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Use bitfields to program MCMAIN timingsAngel Pons
Tested on Asus P8H61-M PRO, still boots. Change-Id: I9a996de5d596cdb541c8b327f119425243724007 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-22nb/intel/sandybridge: Clean up TC_OTHP writesAngel Pons
ODT stretch is configured for both slots in `dram_odt_stretch`. Also drop an unjustified OR, which is setting ODT stretch for one slot. Tested on Asus P8H61-M PRO, still boots. Change-Id: I3a9076afec96e33cfdd12f9b78ca4101b3776dab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47490 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22nb/intel/sandybridge: Use one sequence for write levelingAngel Pons
In order to run a write leveling test, one needs to unset the Qoff bit in MR1, then run the test, and finally set Qoff again. The current IOSAV sequence uses two subsequences to perform the test, while the other two are unused. It is possible to perform the two necessary MR1 updates in the same sequence, which can potentially improve runtime (not measured). Since `write_mrreg` is no longer used, it is necessary to handle address mirroring explicitly. This can be accomplished with the recently-added `ddr3_mirror_mrreg` function, which is also used in `write_mrreg`. Tested on Asus P8H61-M PRO, still boots. Change-Id: I65ca1aa32cdb177d2a9e27c3b02e74ac0c882794 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47614 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-21nb/intel/sandybridge: Introduce `disable_refresh_machine` functionAngel Pons
The same IOSAV sequence is used in both loops, so there's no need to reprogram it again in the second loop. Tested on Asus P8H61-M PRO, still boots. Change-Id: If7ee7917b61e4b752b4fc4700715dc9506520c03 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47612 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20nb/intel/sandybridge: Rename loop variableAngel Pons
The `discover_edges_real` function actually tests a range of values for DQS PI and evaluates how the system responds. Rename the loop variable. Change-Id: I67390ba315d618d153f91c0e8a81db04ec8f63e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47606 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20nb/intel/sandybridge: Remove unnecessary per-rank loopsAngel Pons
The IOSAV_By_BW_MASK_ch registers are not per-rank. To preserve original behavior, use a for-populated-channels loop instead of for-all-channels. Tested on Asus P8H61-M PRO, still boots. Change-Id: I6db35c41cd05420ceaeda93255f5ed73598a5bdd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Rename `discover_edges` functionsAngel Pons
These are simply read MPR training, using the MPR pattern mode in MR3. Change-Id: Icdc60572e0ee0b59dcb5dee1e1aceccfda79f029 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Restore nominal Vref for current channelAngel Pons
After aggressive read training, program nominal Vref for the current channel, not only channel 0. This simple mistake can easily degrade memory margins, especially when running at high speed (overclocking). Tested on Asus P8H61-M PRO, still boots. Change-Id: I12630fe33c5c786c8ec131c45c27180c3887d354 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-11-20nb/intel/sandybridge: Rename `timC_discovery` and relatedAngel Pons
This function simply determines the best delay for the TX DQ PIs. Change-Id: If44c4f661d8c81fe41532ce2bfe3718392b9fe94 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Introduce `ddr3_mirror_mrreg` helperAngel Pons
Write training needs to update mode register 1, but `write_mrreg` will clobber the IOSAV sequence. Reference code uses one four-subsequence to unset Qoff in MR1, run the test, and finally set Qoff again. This will be implemented in future changes, and will use the newly-added helper. Change-Id: I06a06a7bdd43dbde34af4ea2f90e00873eefe599 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Replace and-zero with assignmentAngel Pons
The intent here is to clear the register, so a simple write will work. Change-Id: I547805059e911942ac2cac7bd2165af23d926a2b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Introduce `find_predefined_pattern` functionAngel Pons
Also fuse two per-channel loops together. Tested on Asus P8H61-M PRO, still boots. Change-Id: Iacc66f4364290a66d60d483055abef6e98223d16 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Rename receive enable functionsAngel Pons
Give these functions more meaningful names. Change-Id: I6b308120d4185a3bc448213a925d5cee0d4d8bd9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20nb/intel/sandybridge: Rework timA minmax codeAngel Pons
There's no need to use `struct timA_minmax`, since most cases only care about the difference between logic delay deltas. The final step does use the minimum logic delay across all lanes, but it's a special case. Tested on Asus P8H61-M PRO, still boots. Change-Id: I1da95520ac915ab003e1a839685cbf5f1970eb6a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Correct some whitespace issuesAngel Pons
Add a missing tab and remove spurious spaces in the IOSAV structs. Change-Id: If588d3f01c8744fd0c83576a56cfdda2fb43a3bd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47570 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19nb/intel/sandybridge: Clean up `dram_mr2` functionAngel Pons
Constify variables, and also remove pointless and-masks on mr2reg. Tested on Asus P8H61-M PRO, still boots. Change-Id: I3829012ff7d41f4308ee84d6fbf3b1f2803431af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAMAngel Pons
Reference code never enables SRT for Sandy Bridge, and only enables it for Ivy Bridge when the memory frequency is at most 1066 MHz. Tested on Asus P8H61-M PRO, still boots. Change-Id: I50527f311340584cf8290de2114ec2694cca3a83 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Program MR2 shadow registerAngel Pons
This register must be programmed if Self-Refresh Temperature range is enabled in MR2 (bit 7). Because the memory controller needs to reprogram MR2 when entering Self-Refresh, it needs a copy of the MR2 settings. It also needs to know about mirrored ranks to correctly issue MRS commands. Tested on Asus P8H61-M PRO, still boots. Change-Id: I2e459ac7907ead75826c7d2ded42328286eb9377 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Drop unused `rank` parameterAngel Pons
Change-Id: I5476bbe1a99d087bc026dc5646c8440c50dd151e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47518 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19nb/intel/sandybridge: Relocate `get_ODT` functionAngel Pons
This function is only used in two places, so move its definition closer. Change-Id: I21d3e04de45f58cef0603b6b75119cae4b1a7aae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-11-19nb/intel/sandybridge: Clean up MR0 compositionAngel Pons
There's no need to use and-masks here. Tested on Asus P8H61-M PRO, still boots. Change-Id: If06352daf53ce278dfc64102e023e4f1ea78385c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Rewrite magic numbersAngel Pons
Use bitwise negations for AND-masks and shifts for bitfields. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: Id265728c362a5035ac57f84766e883608f29c398 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47511 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19nb/intel/sandybridge: Remove now-unnecessary sequence macrosAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8H61-M PRO remains identical. Change-Id: I7980daf316cfd524d24df2c10e43b9b15e4e30bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Create sequence helpersAngel Pons
Create some functions to program commonly-used sequences. Tested on Asus P8H61-M PRO, still boots. Change-Id: I1b6474ab208fe5fc2bd7f1b68eff20541fdfce9b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Extract some IOSAV sequences into macrosAngel Pons
This allows deduplicating them while preserving reproducibility. Tested with BUILD_TIMELESS=1, Asus P8H61-M PRO remains identical. Change-Id: Ic7d1a5732296bb678b9954f80508e9f7de7ff319 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Use arrays to program IOSAVAngel Pons
Instead of programming subsequences one-by-one, we might as well take the whole sequence as an array and program all subsequences in one go. Since the number of subsequences is now known in advance, handling of global state can be simplified, which allows reusing the last sequence. Change-Id: Ica1b2b20e04ae368f10aa236ca24d12f69464430 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-19nb/intel/sandybridge: Move IOSAV functions to separate fileAngel Pons
Change-Id: Icbe01ec98995c3aea97bb0f4f84a938b26896fab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16nb/intel/sandybridge: Clarify some parts of raminitAngel Pons
Put names and expand comments for some parts of the code. Change-Id: If1f83bf113ef08469768a9e4dd13819f76633f18 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-11-16nb/intel/sandybridge: Fix typo in commentAngel Pons
Change-Id: I8271911695f41ef7cac1bb228309af0568e5bb0c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16nb/intel/sandybridge: Retype constantAngel Pons
There's no need to use size_t to store a boolean. Change-Id: I0069fa8d75583dc34b402004d753220943406a04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16nb/intel/sandybridge: Drop write_controller_mr() functionAngel Pons
The only reason to write the MR values to the training result registers is for EV (Electrical Validation) usage. The hardware doesn't need it. Tested on Asus P8H61-M PRO, still boots. Change-Id: I808174494729453f4ebcaa13258d735faae68d72 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-16nb/intel/sandybridge: Reduce the scope of get_CWL()Angel Pons
It is only used once, and can thus be moved to the same file. Change-Id: I4ee0621449da7fa1970a475d5a2f6e66546357ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-16nb/intel/sandybridge: Clarify IOSAV_DATA_CTL_ch usageAngel Pons
It is usually written to right after programming a pattern, because its lower byte contains the number of cachelines of the programmed pattern. The other cases merely reset the WDB data write and compare pointers. Change-Id: I97196d404bf70542db28499e0d2e24b7cdab07b6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-11-13mrc_cache: Move code for triggering memory training into mrc_cacheShelley Chen
Currently the decision of whether or not to use mrc_cache in recovery mode is made within the individual platforms' drivers (ie: fsp2.0, fsp1.1, etc.). As this is not platform specific, but uses common vboot infrastructure, the code can be unified and moved into mrc_cache. The conditions are as follows: 1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain switch is true) 2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this means that memory training will occur after verified boot, meaning that mrc_cache will be filled with data from executing RW code. So in this case, we never want to use the training data in the mrc_cache for recovery mode. 3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this means that memory training happens before verfied boot, meaning that the mrc_cache data is generated by RO code, so it is safe to use for a recovery boot. 4. Any platform that does not use vboot should be unaffected. Additionally, we have removed the MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the mrc_cache driver takes care of invalidating the mrc_cache data for normal mode. If the platform: 1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data 2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set BUG=b:150502246 BRANCH=None TEST=1. run dut-control power_state:rec_force_mrc twice on lazor ensure that memory retraining happens both times run dut-control power_state:rec twice on lazor ensure that memory retraining happens only first time 2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig boot twice to ensure caching of memory training occurred on each boot. Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13nb/intel/haswell/acpi: Do not add PEG devices for LPAngel Pons
Haswell Low Power variants do not have PEG at all. Change-Id: Ia5577104b00bfc8713b54c3c43f8dcdd3bc367df Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46791 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13nb/intel/haswell/acpi: Move PEG and CTDP includes downwardsAngel Pons
This change is just to align with Broadwell. Change-Id: I25a481503f5df79502f5ae60c87e7dacb781adad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46790 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`Angel Pons
Tested with BUILD_TIMELESS=1, Google Wolf remains identical. Change-Id: I710581156937b042ba4cf5948c65d0795ad37bbf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46789 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13nb/intel/haswell/acpi/hostbridge.asl: Drop unused registersAngel Pons
These are not used anywhere and are not present on Broadwell. Change-Id: I2d1359286ac719cb5daefc955d5c6085e2949c1f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46788 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVENAngel Pons
There's no need to perform manual shifting and masking when ACPI allows one to painlessly describe bitfields of a register. The now-unused DVEN definition will be dropped in a follow-up, alongside other definitions. Change-Id: Iab6972c78c1114c8e3dfee28320ae233421ff154 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46787 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13haswell/lynxpoint: Drop remaining uses of `ISLP` methodAngel Pons
There's no need to dynamically differentiate between traditional and Low Power platforms at runtime, and doing so makes code reuse more complex. Change-Id: Id40f2f5f41db00487af9115eabee8874c2399030 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46785 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09nb/intel/pineview: Fix clearing memoryArthur Heymans
The regions TSEG, GSM, GMS should not be marked as cacheable resources. Change-Id: I083b096cf3ed250bca722674abe9feffdb2436d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-04haswell: Add Intel TXT support in romstageAngel Pons
Provide necessary romstage hooks to allow unblocking the memory with SCLEAN. Note that this is slow, and took four minutes with 4 GiB of RAM. Tested on Asrock B85M Pro4 with tboot. When Linux has tboot support compiled in, booting as well as S3 suspend and resume are functional. However, SINIT will TXT reset when the iGPU is enabled, and using a dGPU will result in DMAR-related problems as soon as the IOMMU is enabled. However, SCLEAN seems to hang sometimes. This may be because the AP initialization that reference code does before SCLEAN is missing, but the ACM is still able to unblock the memory. Considering that SCLEAN is critical to recover an otherwise-bricked platform but is hardly ever necessary, prefer having a partially-working solution over none at all. Change-Id: I60beb7d79a30f460bbd5d94e4cba0244318c124e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-04nb/intel/haswell: Place CTDP ASL code in a separate scopeAngel Pons
This is just to align the code with what Broadwell does. Change-Id: I52fb1546d049ca9fa09d0c54304ca1d79f6c4c3e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46756 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04nb/intel/haswell/acpi: Align with BroadwellAngel Pons
Align cosmetics and move CTDP-specific ASL into its own file. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I476a4e01016caa3658177b0fa8916576f4a5e0e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46755 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-31{cpu,nb}/intel/haswell: Drop unnecessary `UL` suffixAngel Pons
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: I029ab0dccbf7b61d641cccf79b491fabf97ab74a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46720 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26src: Include <arch/io.h> when appropriateElyes HAOUAS
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25nb/intel/haswell/gma.c: Drop unused ChromeOS includeAngel Pons
Change-Id: I598fe743354ea429d6821b95be7d209a9fcf9f0c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46693 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-25nb/intel/haswell/gma.c: Drop unused `set_translation_table` functionAngel Pons
Change-Id: I6c65a5a74a83b8da299245fd6f4a7ae7c1ed30c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46692 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/haswell/gma.c: Drop space after unary `!`Angel Pons
Change-Id: I72f75f3df50af362874818f2c1883a6a1c741087 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46691 Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/haswell/gma.c: Move log message to the right placeAngel Pons
The message was being printed too early, possibly because it was relocated around alongside the rest of the code. Change-Id: I4257f6f0baa1c398aa1df9bd3274458abfaf28a6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46690 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/haswell/gma.c: Use `config_of` in `gma_setup_panel`Angel Pons
This is to reduce differences between Haswell and Broadwell. Change-Id: I8d6a8ee02e24bee22f0a7b69098ea8430095ba90 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-10-24nb/intel/haswell/early_init.c: Remove invalid register writesAngel Pons
MRC does not use the value of SSKPD, and will overwrite it with constant values at the end of memory initialisation. Since coreboot does not rely on this particular bit's value, it is safe to drop the writes to set it. MCHBAR register 0x6120 is undocumented. It is nowhere to be found in any documentation or code I have access to; not even for Sandy/Ivy Bridge, the platform where this mysterious register write originally came from. These workarounds were copied from Sandy Bridge, but do not apply to Haswell. They were dropped on Broadwell, so drop them for Haswell too. Tested on Asrock B85M Pro4, still boots. Change-Id: I21d9656a7595d47ac8648c08d223b7cbafd213c3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46683 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/haswell/finalize.c: Align with BroadwellAngel Pons
Reorder register writes to match the locking order in Broadwell. Tested on Asrock B85M Pro4, still boots and registers are still locked. Change-Id: Ibe15c2598fabda752c9a54eba6362621e144ad77 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46682 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/haswell/finalize.c: Align MC locking with BroadwellAngel Pons
Broadwell uses a 32-bit or, so also use it on Haswell for consistency. This has no effect because MRC already locks the memory controller down. Tested on Asrock B85M Pro4, still boots and register is still locked. Change-Id: Ida69cd9a95a658c24b4d2558dde88b94c167a3f9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46681 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/haswell/finalize.c: Lock down MC ARB registerAngel Pons
The Haswell System Agent BIOS Spec revision 0.6.0 indicates this register needs to be locked, and Broadwell already locks it. Tested on Asrock B85M Pro4, still boots and register is locked. Change-Id: Icdeb39e2fdde1403b6ab83faed214addca863f4b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46680 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/haswell/finalize.c: Lock PCU DDR PTMAngel Pons
This register has a lock bit. The Haswell System Agent BIOS Spec revision 0.6.0 indicates it needs to be set, thus set it. Note that Broadwell already locks this register. Tested on Asrock B85M Pro4, still boots and register is locked. Change-Id: Ie23b825e708edbfc04ec0d7783f868e8632eb608 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46679 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/haswell/finalize.c: Drop obsolete SA PM lockAngel Pons
This register had a lock bit on Sandy Bridge, but does not on Haswell. Moreover, the bit remains cleared on Asrock B85M Pro4 with coreboot. Therefore, remove the write to this bit, because it has no effect. Tested on Asrock B85M Pro4, still boots. Change-Id: I382a6d69233ced5af069767eb61b56741ed665be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46678 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/haswell/finalize.c: Use PCI register namesAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I46331225f36a58615c9cb67d6387fd020d30a04d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46677 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/gm45: Clean up header handlingAngel Pons
There's no need to have ACPI guards in `gm45.h`, since the only things the ASL files require are the base address definitions in `memmap.h`. Also, remove the southbridge include from `gm45.h` and place it only in the files that actually require something from it. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Ica2c5ae9f57595c8577a1bfcc3b57f2c57b3e980 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45452 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/gm45: Introduce memmap.hAngel Pons
Move all memory map definitions into a separate header. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Idddb63069b7a0b7b4d6c7850473a71318748bb9b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-24nb/intel/gm45: Add more DMIBAR/EPBAR registersAngel Pons
Add definitions for more DMIBAR/EPBAR registers, and specify their sizes as well. Also, expand a comment as the registers' purpose is now known. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I9687d34e0663e70bdd2a1aa682246c2448690e18 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45448 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/ironlake: Add more host bridge PCI IDsAngel Pons
The host bridge PCI device ID can be changed by the firmware. There is no documentation about it, though. There's 'official' IDs, which appear in spec updates and Windows drivers, and 'mysterious' IDs, which Intel doesn't want OSes to know about and thus are not listed. The current coreboot code seems to be able to change the device ID of the host bridge, but it seems to be missing a warm reset so that the device ID changes. Account for the 'mysterious' device IDs in the northbridge driver, so that booting an OS has a chance to work. For the sake of completeness, add the PCI device IDs for Clarkdale. Although only Arrandale is known to work, both of them are Ironlake. It is possible that the Management Engine handles changing the PCI device ID, which would not happen when using a broken ME firmware. Change-Id: I93c9c47e2b0bf13d80c986c7d66b6cdf0e192b22 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45562 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-24nb/intel/ironlake: Generalise northbridge chip nameAngel Pons
The code is known to work on processors other than just i7's. Also, use the northbridge's name (Ironlake) in place of the CPU's (Arrandale). Change-Id: Ia33fa285b4bacd652932d2187384ca1814c9528a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>