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Change-Id: I1095944e65bfacd9e878840cc88f8a0a24ecde72
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: Id1ed2252ce3ed052730dd10b24c453c34c2ab4ff
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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DIMMB's DDR width is in bit 20, not bit 19.
Change-Id: I48866d9243c2a576a02519724429801ae47c5644
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.
Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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DISPPLANE_BGRX888 defined in drivers/intel/gma/i915_reg.h
included in i915.h file
Change-Id: I4e9414f39a29e4eac7e325672ce6520a5654d3bc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ic01bbae9acaabaade777db52825aa80d25fc5961
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The ALSB gnvs variable is used to load the OpRegion memory
address into the ASLS register on the S3 resume path, and must
therefore first be set on the normal boot path.
This patch brings Haswell in line with SNB/IVB/Nehalem, which
already save the OpRegion address in ASLB.
Change-Id: Ie062cbfe7e7f60c2a4e2b9111f6b6da87ced7a39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Problem was introduced by fb2f667da2 "nb/amd/amdk8: Link raminit_f.c"
which linked debug.c and was not tested with this option.
Change-Id: I8597a6915c65ea783a864110cb23ecb34ea0611b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Swift Geek <swiftgeek@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Needed to generate cpu entries.
Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I56cb941d07ac48f8209a892ec18af8f5090765f7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Code checked manually
Change-Id: Idf86546ddda4fa2b4b96f0b703c03af9931c757d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This requires to also unify the calling convention for
AGESA functions from
AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
to
AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr)
On systems running 32bit x86 code this will not make a difference as
UINTN is uintptr_t which is 32bit on these machines.
Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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It's pretty obvious that the author did not want to use a logical
and (&&) here but an arithmetical and (&)
Change-Id: Ic1bece86986906b76308bbb46235c22418e27990
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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dual_node is never used in that function. And it is never set
correctly either, because the register f3xe8 is never actually
read either. Just remove the whole useless construct.
Change-Id: If316da89bceae6b162f20e4b632276db2d9ef423
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Fill in acpi_name to return proper ACPI names. To be used with
SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
GFX0 is used in drivers/intel/gma/acpi/pch.asl.
MCHC is used in nb/intel/sandybridge/acpi/hostbridge.asl.
Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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Copy northbridge files from northbridge/amd/pi/00670F00
to soc/amd/stoneyridge and soc/amd/common.
Changes:
- update chip_ops and device_ops
- remove multi-node support
- clean up Kconfig and Makefile
Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and
soc/amd/common. This is the second patch in the process of
converting Stoney Ridge to soc/.
Changes:
- update Kconfig and Makefiles
- update vendorcode/amd for new soc/ path
Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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On boards that are able to take two DIMMs per channel the
command rate should be 2T. It is possible to use 1T with
load reduced "1T" DIMMs, but it's not clear how to detect
those DIMMs. Raminit might fail for those who do not have
such DIMMS installed.
Hardcode command rate of 2T to make sure raminit works on
dual DIMM per channel boards (currently only desktop boards).
The command rate of 1T is still tested if only 1 DIMM per
channel is present.
Will decrease performance on quad slot mainboards, if two DIMMs
are installed in one channel and previously 1T have been selected.
Tested on ASRock B75 Pro3-M.
Change-Id: I029d01092fd0e11390cebcd94ca6f23bf0ee2cab
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Maybe we could go on, but cbmem_add() failing is a very bad sign.
Should fix coverity CID 1376384 (Null pointer dereferences
(NULL_RETURNS)).
Change-Id: I330cee6db3540c6a9c408d56da43105de5d075f7
Found-by: Coverity Scan #1376384
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20280
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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These delays, adding up to 600 ms, don’t seem to be needed, so remove
them.
TESTED on d510mo, boots fine without.
Change-Id: If089d6677fe95b086eeb00540acfbb66fa2e1c47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
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Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older
Haswell MRC binary doesn't populate the pei_data struct with
all the info needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use common init_igd_opregion method and remove duplicated code in
acpi.c.
Change-Id: I811e8bd2be68813321dc4581af02e1c21b0da076
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add method gma_write_acpi_tables.
No need to update GNVS as it doesn't have ASLB.
Change-Id: Ia138cfde2271a298c36b85e999ff69f0f211ba11
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This was the single spot where VGA_BIOS_ID wasn't guarded by anything.
It resulted in the wrong default id if we didn't chose to add a VGA BIOS
at first but added one later (e.g. a board provided default guarded by
VGA_BIOS wasn't applied then, because the Via/CN700 value was already
set).
Change-Id: Ia16a5e6d194191d8da8c551d6eb3849bc65864a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use common init_igd_opregion method.
Change-Id: Ia10a28d05b611a59f787b53f9736b3b76a19ea4a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Use common init_igd_opregion method.
Change-Id: Ic8a85d1373f04814b4460cce377d6e096bcdc349
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
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Too low gfx_uma_size can result in problems if the framebuffer
does not fit.
This partially reverts: 7afcfe0 "gm45: enable setting all vram sizes
from cmos"
Change-Id: I485d24198cb784db5d2cfce0a8646e861a4a1695
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Also changes the arguments of some functions to const.
This reduces romstage size by a whopping 1009 bytes.
Change-Id: I054504412524b7be19d98081097843b61bc0c459
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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There are many good reasons why we may want to run some sort of generic
callback before we're executing a reset. Unfortunateley, that is really
hard right now: code that wants to reset simply calls the hard_reset()
function (or one of its ill-differentiated cousins) which is directly
implemented by a myriad of different mainboards, northbridges, SoCs,
etc. More recent x86 SoCs have tried to solve the problem in their own
little corner of soc/intel/common, but it's really something that would
benefit all of coreboot.
This patch expands the concept onto all boards: hard_reset() and friends
get implemented in a generic location where they can run hooks before
calling the platform-specific implementation that is now called
do_hard_reset(). The existing Intel reset_prepare() gets generalized as
soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now
easily be added later if necessary). We will also use this central point
to ensure all platforms flush their cache before reset, which is
generally useful for all cases where we're trying to persist information
in RAM across reboots (like the new persistent CBMEM console does).
Also remove cpu_reset() completely since it's not used anywhere and
doesn't seem very useful compared to the others.
Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19789
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The previous code seemed weird and tried to check if its selected
value is supported three times.
This also lower the clock if a selected frequency does not result in a
supported CAS number.
Change-Id: I1df20a0a723dc515686a766ad1b0567d815f6e89
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The previous code seemed weird and tried to check if its selected
value is supported three times.
This also lower the clock if a selected frequency does not result in a
supported CAS number.
Change-Id: I97244bc3940813c5a5fcbd770d71cca76d21fcae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Use common init_igd_opregion method.
Change-Id: Ie70a49fd532b7ad7679dc558cc4a019a273a0602
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Copy Haswell's init_igd_opregion to common folder.
Remove platform specific code.
Will replace all Intel NB implementations.
Change-Id: I14dfb5986df264ffd71183a159f98b79e8e3230e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Switch from lapic to tsc.
Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.
Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.
Tested on Lenovo T430.
Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Provide all gfx init methods as a Kconfig `choice`. This elimates the
option to select native gfx init along with running a Video BIOS. It's
been only theoretically useful in one corner case: Hybrid graphics
where only one controller is supported by native gfx init. Though I
suppose in that case it's fair to assume that one would use SeaBIOS to
run the VBIOS.
For the case that we want the payload to initialize graphics or no
pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the
choice. If multiple options are available, the default is chosen as
follows:
* NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS,
* VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS,
* NATIVE_VGA_INIT, if we don't add a Video BIOS.
As a side effect, libgfxinit is now an independent choice.
Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the
reference clock can be 100Mhz.
Decode the register and use the reference clock to calculate
the selected DDR frequency.
Tested on Lenovo T430.
Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put
it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are
two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt
and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for
`HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model
that with additional symbols.
Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers
that support a linear framebuffer. Some related settings moved to the
drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are
hardcoded.
Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.
Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Specification says to do CAR teardown as part of AmdInitPost().
Move initializing the final AGESA heap storage to AmdInitEnv()
so that its work is not lost even if AMD_DISABLE_STACK does
invalidation without writeback.
Change-Id: Icf0ec74c390e60122d0b312b5f09f46bb930e085
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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|
Via/VX800 was the last chip not defining it.
Change-Id: Idd03f48bed881a5846b1bb3bf29254450d6cff3b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The deprecated LATE_CBMEM_INIT function is renamed:
set_top_of_ram -> set_late_cbmem_top
Obscure term top_of_ram is replaced:
backup_top_of_ram -> backup_top_of_low_cacheable
get_top_of_ram -> restore_top_of_low_cacheable
New function that always resolves to CBMEM top boundary, with
or without SMM, is named restore_cbmem_top().
Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
It could end up not initialized which causes it not to build with
clang.
Change-Id: I3be9477d836123aaa87c9bebb41c1ec34689a771
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I3cd5e99b9954a68837de85b49b4389b668e00cf4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
This makes the code more readable since it avoids messing with two
dimensional arrays and needing remember what the indices mean.
Also introduces an unused coarse element which is 0 for all default
DLL settings on DDR2.
Change-Id: I28377d2d15d0e6a0d12545b837d6369e0dc26b92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Hides JEDEC steps using the RAM_SPEW macro.
Also hides a hexdump of SPDs.
Change-Id: Ie2b484cf1f1d296823df0473e852d9d07ca20246
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This improves readability.
Change-Id: Ib4387a4f4092053dab273191a73edb0ef31a79f6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
It is not really known why there is such a long delay, but it works
fine without it.
TESTED on ga-g41m-es2l.
Change-Id: Idff5b978bbf161f8520d8000848e7b11c98c3945
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19514
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Hide device 4 and device 7 if disabled.
Allows devicetree settings to take effect.
Tested on Lenovo T430.
Change-Id: I64a19e2bbdb1640e1d732f6e4486f73cbb0bda81
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.
Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.
Change-Id: I0c375e5da0dfef6cef0c50272356cd32a87b1ff6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Vendorcode decides already in AMD_INIT_POST the exact location
of UMA memory. To meet alignment requirements, it will extend
uma_memory_size. We cannot calculate base from size and TOP_MEM1,
but need to calculate size from base and TOP_MEM1 instead.
Also allows selection of UmaMode==UMA_SPECIFIED to manually set
amount of memory reserved for framebuffer.
Change-Id: I2514c70a331c7fbf0056f22bf64f19c9374754c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
A left-over from 5e3cb72a71 (nb/x4x: Do not enable IGD when not
supported). Should fix coverity issue 1375009. Remove a redundant
line that uses the variable `gfxsize` out of its scope and move the
variable declaration. Make sure the variable is always initialized,
drop unneeded error-handling for `get_option()` and sanitize the
read value instead.
Change-Id: Iee2beda30d8c74df0f412622c3ff3357819e386b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19680
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
`cardF[n]` should indicate whether the DIMM in channel n is of
raw card type F. However, `cardF[1]` was initialised with the
value meant for `cardF[0]`. This patch results in the correct
initialisation of `cardF`.
Tested on a Lenovo T400 containing two DIMMs: one of raw card
type F and the other of raw card type B. Before the patch, the
system would not boot. After the patch, the system boots with all
of the memory functional.
Change-Id: I7409df0b8c67d7efbdadae39dc718c8df7a92552
Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Reviewed-on: https://review.coreboot.org/19652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This results in raminit_receive_enable_calibration.c producing
no errors or warnings with checkpatch.
The issues fixed are:
ERROR: that open brace { should be on the previous line
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
Tested by compiling after making the changes.
Change-Id: I8d2f4f1fe2f17aa44c0a7090c178eee418defe78
Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Reviewed-on: https://review.coreboot.org/19651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I5322d731a0dc655f2da14b87fa6cbc1e54b5abd5
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/18522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Currently only one board uses this northbridge in coreboot but some
patches are pending to add more.
Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I2308b069b8f2c601254169bcb6a34442c537a311
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I15550b1cc1a7ccfecba68a46ab2acaee820575b9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Is only present on the P45 subtype of chipset.
Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
According to "Intel ® 4 Series Chipset Family datasheet" in the
description about GGC and DEVEN, CAPID0 bit46 is said to reflect the
presence of an internal graphic device. This would allow the P43 and
P45 chipset variants to work.
Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18515
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The NGI writes to legacy VGA registers which should not happen when
VGA cycles are assigned to a different device.
TESTED on ga-g41m-es2l
Change-Id: I0a03e35c0d7f2532edd6cc5e62d1cf07dab57f60
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This disables VGA cycles on IGD when an external VGA device is
found. This allows PCI or PCIe devices to be the 'main' VGA device if
found, while the IGD is still available.
TESTED on ga-g41m-es2l: SeaBIOS shows payload on external GPU while
linux (4.10) can use both as a framebuffer simultaneously without any
extra configuration.
Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Computes TSEG size dynamically.
Changes the size of legacy hole to match other Intel northbirdges.
Refactor this a little by needing one less variable.
Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This code ought not to run if ME is disabled. It also prohibits
writing to some GMCH regs like GGC bit1.
Intel ® 4 Series Chipset Family datasheet refers to this as
"ME stolen Memory lock" without actually describing this
functionality.
Change-Id: Iaa8646e535e13c44c010ccd434a5af954cf7dfbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Use names instead of magic values.
No functional change.
Change-Id: I3774595ff0fd21e42dc407ca8a0cf3fd7788a66f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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Use register name instead of hex value.
No functional change.
Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
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The checkreset() function checks if raminit previously
succeeded (pmcon2 bit7 == 0). If this is not the case it will issue a
hot reset (writing 0x6 to 0xcf9). On the next attempt to boot the
system BOOT_PATH_RESET path will be taken. This boot path can only
successfully initialize memory if the system was reset from a state
where raminit succeeded, which is not the case here.
This can be fixed by issuing a cold reset instead of a hot reset.
Change-Id: Idbcf034c3777a64cc3fb92dc603d10470a6c8cb6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add some known good values for some thinkpads displays.
Known good means that at this pwm frequency the display is evenly lit
on all duty cycles, the display makes minimal to no noise at lower
duty cycles and the display does not flicker. This values differs from
vendor (which uses an obviously wrong display clock (190MHz instead
of 320MHz) resulting in frequency more than 60% off the intended
value.
TESTED on Thinkpad X200 with edid ascii string in list and removed
from list to see if notice message is shown.
Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This allows to use EDID data outside of NGI path without needing to
fetch it twice.
Change-Id: I6a540b1d036a9f38b44fd004309601630861f6e7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Claim memory-mapped regions in the legacy area.
Claim an MMIO resource for the A000 and B000 segments, and reserved
resource for C000 through F000 segments.
These changes allow code and information to be retained in the event
unused regions get wiped.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit d612d4fe69881609d42053496409c452e1014947)
Change-Id: I9c47c919bbfd0edccf752e052f32d1e47c1a1324
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19156
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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|
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: I97c3402ac055991350732e55b0dda042b426c080
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: I76b31fe5fd19b50b82f57748558fb04408e0fd23
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19309
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: Ie5d93117ee8bd8d15085aedbfa7358dfcf5f0045
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19307
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I1ef1323dc1f3005ed194ad82b75c87ef41864217
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19367
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This needs some extra headers in amdk8/raminit.c that were otherwise
provided by that file.
Change-Id: I80450e5eb32eb502b3d777c56790db90491fc995
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19360
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Add a check for vboot when locating the binaryPI image.
There is currently an ordering problem using cbmem to locate the
image when vboot is present. Vboot inserts its locator into the
search process so that memory can be checked before flash is queried.
For the earliest calls using the wrapper, DRAM has not been set up
and cbmem not initialized in romstage. This change prevents an
endless loop when vboot searches cbmem.
This change has another side effect. When vboot is in effect, the
change forces the RO binaryPI to be used even when on either of the
RW paths. There is currently no ability to relocate the XIP image
for use in a RW region.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474)
Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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For this debug.c needs to be linked too.
Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This is not needed.
Change-Id: Id19a00c1546b7a71d90aa8c7e43e6efde1e9fbbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19425
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19333
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Id1b7b98b4fba745ac0d55638b6a5cceba3c329ef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19415
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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TESTED on D510MO.
Change-Id: I05aa40df0d2a090fcf734416669e9e1bbff094e4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19414
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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For raminit to succeed on a hot reset the following things are
prevented from running:
* Clearing self refresh
* Setting memory frequency
* programming sdram dll timings
* programming rcomp
TESTED on Intel d510mo.
Change-Id: I8f7e5c2958df29a96cdf856ade2f4f33707ad362
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19337
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Clean up NGI code now that libgfxinit has replaced old C code:
- replace #if preprocessor guards with if (IS_ENABLED(...))
- don't guard variable declarations
- remove code that would only be executed for old NGI / isn't
used by libgfxinit
Test: boot google/wolf with VBIOS, NGI, and UEFI/GOP video init,
observe payload and pre-OS graphics display functional.
Change-Id: I96e74f49ea70e09cbac6f8af561de3e18fa7d260
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19327
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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The function decode_spd uses undeclared variables and an incorrectly
initialized array.
Change-Id: Ib45a8b2946c04c270e29524675b1f09d491d282b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19336
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ib92550fe755293ce8c65edf59242a2b04327128e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19332
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
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Hide some (partial) lines behind DEBUG_RAM_SETUP and shorten
some messages. This saves some KiB to make CBMEM console more
usable in romstage.
Change-Id: I62a84ca662ee778b7c1deb71247f3b01a37858fa
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Adds the necessary plumbing for acpi_device_path() to find the LPC
bridge on the AMD Family10h/15h northbridges and SB700 southbridge.
This is necessary for TPM support since the acpi path to the LPC bridge
doesn't match the built-in default in tpm.c
This is a port of GIT hash d8a2c1fb by Tobias Diedrich.
BUG=https://ticket.coreboot.org/issues/102
Change-Id: I1c514e335e194b2864599e5419cfaee830b94e38
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/19282
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Don't #include *. but use linker.
Change-Id: I716b37e71ab3a4409709357f50f79e3149ede2b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19027
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The x4x northbridge can be paired with either an ICH7 (in the case of
g41) or an ICH10 (all other cases: g45, q45, p45, ...). Only ICH10
sometimes occurs with a descriptor, gbe and an ME region.
ICH7 is always descriptorless so it makes no sense to fix CBFS to
accommodate for those other objects.
Change-Id: I4a01dfdbce1807e44932a3ac812110382332abd8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19181
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: Ie046fd3c413585131669193a6669358adf709028
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19268
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Includes the DRAM controller device that knows which where the division
between addresses routed to the main memory and to the PCI bus is.
Change-Id: Id4cfeb8ff32de37723eee68a61c576e657dad30b
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18896
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This is the actual PCI Id of the internal graphics.
Change-Id: I2a25ed35a5b01de6da905619fa9fce96738d1c0e
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18895
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Without them the BS_DEV_RESOURCES stage won't traverse the bridge and
the graphics controller would be left without resources assigned.
Even worse, the resources would stay based in offset 0 which confuses
the MTRR setting code and causes a good chunk of the DRAM to be set
to type write combining.
With the patch applied, the resources are set:
Show resources in subtree (Root Device)...After assigning values.
...
PCI: 00:01.0 child on link 0 PCI: 01:00.0
+ PCI: 00:01.0 resource base ffff size 0 align 0 gran 0 limit ffff flags 60080100 index 0
+ PCI: 00:01.0 resource base f8000000 size 4000000 align 26 gran 0 limit fbffffff flags 60081200 index 1
+ PCI: 00:01.0 resource base fc000000 size 1010000 align 24 gran 0 limit fd00ffff flags 60080200 index 2
PCI: 01:00.0
- PCI: 01:00.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10
- PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14
- PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
+ PCI: 01:00.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10
+ PCI: 01:00.0 resource base fc000000 size 1000000 align 24 gran 24 limit fcffffff flags 60000200 index 14
+ PCI: 01:00.0 resource base fd000000 size 10000 align 16 gran 16 limit fd00ffff flags 60002200 index 30
And the caching mode is set properly:
MTRR: Physical address space:
-0x0000000000000000 - 0x0000000004000000 size 0x04000000 type 1
-0x0000000004000000 - 0x000000000e000000 size 0x0a000000 type 6
-0x000000000e000000 - 0x0000000100000000 size 0xf2000000 type 0
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x000000000e000000 size 0x0df40000 type 6
+0x000000000e000000 - 0x00000000f8000000 size 0xea000000 type 0
+0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1
+0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0
The problem was also spot and discussed here:
http://coreboot.coreboot.narkive.com/E9eGauzH/via-c7-on-bcom-winnet-p680-l1-l2-cache-very-slow
Change-Id: Idb4979b206838dd6455b2a16de14dc74f83af921
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18894
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Otherwise, it locks up quickly. Not sure which ones are actually needed
and why, couldn't bisect it into removing even a single one.
The factory BIOS on a Neoware G170 does 200 0xed reads between setting
the registers too.
Change-Id: I6aa38768d84dd42c9c720c917a99e6b4b1e03427
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18893
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203).
Not running PCIEx16 init which is valid for 945gm seems to fix all
issues and instabilities related to the PEG port.
According to lspci the link width is at the desired x16.
It is unknown if devices requesting a lower width work automatically
or need more configuration.
What happens is that IGD gets disabled by the disable function in
gma.c when an external GPU is found unless
CONFIG_ONBOARD_VGA_IS_PRIMARY is set.
Setting IGD as secondary makes Linux (4.10) hang, so this behavior is
a requirement for now.
TESTED on P5GC-MX with a discrete GPU and both
CONFIG_ONBOARD_VGA_IS_PRIMARY set and unset.
Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18549
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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