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path: root/src/northbridge
AgeCommit message (Expand)Author
2021-01-06nb/intel/sandybridge: Define and use `QCLK_PI` constantAngel Pons
2021-01-05nb/intel/haswell/memmap.h: Clean upAngel Pons
2021-01-04nb/intel/sandybridge: Replace memset with initializerAngel Pons
2021-01-01nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settingsMichael Niewöhner
2021-01-01soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representationMichael Niewöhner
2020-12-30drivers/intel/gma: Include gfx.asl by default for all platforms...Matt DeVillier
2020-12-29soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delayMichael Niewöhner
2020-12-28kconfig: remove non-existent sourceJack Rosenthal
2020-12-25cpu/intel/model_206ax: Add more CPU steppingsAngel Pons
2020-12-25nb/intel/sandybridge: Move steppings to CPU headerAngel Pons
2020-12-25nb/intel/sandybridge: Rewrite constant valuesAngel Pons
2020-12-25nb/intel/sandybridge: Allow to ignore XMP voltageAngel Pons
2020-12-23nb/intel/sandybridge: Refactor ODT stretch table codeAngel Pons
2020-12-23nb/intel/sandybridge: Refactor `dram_find_spds_ddr3`Angel Pons
2020-12-23nb/intel/sandybridge: Always wait for IOSAV after starting itAngel Pons
2020-12-23nb/intel/sandybridge: Introduce `iosav_run_once_and_wait`Angel Pons
2020-12-23nb/intel/sandybridge: Remove unnecessary commentsAngel Pons
2020-12-23nb/intel/sandybridge: Print delays in decimalAngel Pons
2020-12-23nb/intel/sandybridge: Add comment to TC_RWP writeAngel Pons
2020-12-23nb/intel/sandybridge: Use proper names to refer to training stepsAngel Pons
2020-12-23nb/intel/sandybridge: Add comments about I/O and RT latencyAngel Pons
2020-12-23nb/intel/sandybridge: Rename I/O data timingsAngel Pons
2020-12-23nb/intel/sandybridge: Use bitfields for I/O data timingsAngel Pons
2020-12-23nb/intel/sandybridge: Compute data timings independentlyAngel Pons
2020-12-17drivers: Replace set_vbe_mode_info_validPatrick Rudolph
2020-12-14nb/intel/ironlake: Add comment about MCH scan chainsAngel Pons
2020-12-14nb/intel/ironlake: Remove unused constantAngel Pons
2020-12-13nb/intel/sandybridge: Clean up program_timingsAngel Pons
2020-12-12nb/intel/sandybridge: Clean up stepping logicAngel Pons
2020-12-12nb/intel/sandybridge: Fix blunder in MR2 shadow codeAngel Pons
2020-12-07nb/intel/ironlake: Introduce memmap.hAngel Pons
2020-12-07nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
2020-12-07nb/intel/i945: Introduce memmap.hPatrick Georgi
2020-12-03cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()Julius Werner
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
2020-12-02cbfs: Enable CBFS mcache on most chipsetsJulius Werner
2020-11-25nb/amd: Deduplicate nb_common.hAngel Pons
2020-11-25device: Drop unused HyperTransport codeAngel Pons
2020-11-23nb/amd/agesa/family15tn: define macros for GNB and IOMMU devicesMike Banon
2020-11-23nb/amd/agesa/family15tn: define macro for internal HDMI audio controllerMike Banon
2020-11-22nb/amd/pi: Remove 00660F01 directory & filesMartin Roth
2020-11-22cpu/amd/pi: Remove unused cpu code 00660F01Martin Roth
2020-11-22nb/intel/sandybridge: Clean up COMPOFST1 logicAngel Pons
2020-11-22nb/intel/sandybridge: Correct get_COMP2 functionAngel Pons
2020-11-22nb/intel/sandybridge: Rename and refactor `discover_timC_write`Angel Pons
2020-11-22nb/intel/sandybridge: Only use write Vref if supportedAngel Pons
2020-11-22nb/intel/sandybridge: Refine power-down mode logicAngel Pons
2020-11-22nb/intel/sandybridge: Lower tPRPDEN to 1Angel Pons
2020-11-22nb/intel/sandybridge: Increase tRWDRDD with fast RAMAngel Pons
2020-11-22nb/intel/sandybridge: Rename and clean up `discover_edges_write`Angel Pons
2020-11-22nb/intel/sandybridge: Relocate PREA-ACT-RD sequenceAngel Pons
2020-11-22nb/intel/sandybridge: Remove spurious writes to IOSAV BW maskAngel Pons
2020-11-22nb/intel/sandybridge: Drop `precharge` functionAngel Pons
2020-11-22nb/intel/sandybridge: Clarify register writeAngel Pons
2020-11-22nb/intel/sandybridge: Encapsulate JEDEC write levelingAngel Pons
2020-11-22nb/intel/sandybridge: Do not rewrite write leveling sequenceAngel Pons
2020-11-22nb/intel/sandybridge: Make helper for write leveling sequenceAngel Pons
2020-11-22nb/intel/sandybridge: Run `read_mpr_training` before write trainingAngel Pons
2020-11-22nb/intel/sandybridge: Rename `read_training` functionAngel Pons
2020-11-22nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD registerAngel Pons
2020-11-22nb/intel/sandybridge: Use bitfield for GDCRCMDPICODINGAngel Pons
2020-11-22nb/intel/sandybridge: Move constants out of for-loopAngel Pons
2020-11-22nb/intel/sandybridge: Use bitfields to program MCMAIN timingsAngel Pons
2020-11-22nb/intel/sandybridge: Clean up TC_OTHP writesAngel Pons
2020-11-22nb/intel/sandybridge: Use one sequence for write levelingAngel Pons
2020-11-21nb/intel/sandybridge: Introduce `disable_refresh_machine` functionAngel Pons
2020-11-20nb/intel/sandybridge: Rename loop variableAngel Pons
2020-11-20nb/intel/sandybridge: Remove unnecessary per-rank loopsAngel Pons
2020-11-20nb/intel/sandybridge: Rename `discover_edges` functionsAngel Pons
2020-11-20nb/intel/sandybridge: Restore nominal Vref for current channelAngel Pons
2020-11-20nb/intel/sandybridge: Rename `timC_discovery` and relatedAngel Pons
2020-11-20nb/intel/sandybridge: Introduce `ddr3_mirror_mrreg` helperAngel Pons
2020-11-20nb/intel/sandybridge: Replace and-zero with assignmentAngel Pons
2020-11-20nb/intel/sandybridge: Introduce `find_predefined_pattern` functionAngel Pons
2020-11-20nb/intel/sandybridge: Rename receive enable functionsAngel Pons
2020-11-20nb/intel/sandybridge: Rework timA minmax codeAngel Pons
2020-11-19nb/intel/sandybridge: Correct some whitespace issuesAngel Pons
2020-11-19nb/intel/sandybridge: Clean up `dram_mr2` functionAngel Pons
2020-11-19nb/intel/sandybridge: Limit SRT to Ivy Bridge and slow RAMAngel Pons
2020-11-19nb/intel/sandybridge: Program MR2 shadow registerAngel Pons
2020-11-19nb/intel/sandybridge: Drop unused `rank` parameterAngel Pons
2020-11-19nb/intel/sandybridge: Relocate `get_ODT` functionAngel Pons
2020-11-19nb/intel/sandybridge: Clean up MR0 compositionAngel Pons
2020-11-19nb/intel/sandybridge: Rewrite magic numbersAngel Pons
2020-11-19nb/intel/sandybridge: Remove now-unnecessary sequence macrosAngel Pons
2020-11-19nb/intel/sandybridge: Create sequence helpersAngel Pons
2020-11-19nb/intel/sandybridge: Extract some IOSAV sequences into macrosAngel Pons
2020-11-19nb/intel/sandybridge: Use arrays to program IOSAVAngel Pons
2020-11-19nb/intel/sandybridge: Move IOSAV functions to separate fileAngel Pons
2020-11-16nb/intel/sandybridge: Clarify some parts of raminitAngel Pons
2020-11-16nb/intel/sandybridge: Fix typo in commentAngel Pons
2020-11-16nb/intel/sandybridge: Retype constantAngel Pons
2020-11-16nb/intel/sandybridge: Drop write_controller_mr() functionAngel Pons
2020-11-16nb/intel/sandybridge: Reduce the scope of get_CWL()Angel Pons
2020-11-16nb/intel/sandybridge: Clarify IOSAV_DATA_CTL_ch usageAngel Pons
2020-11-13mrc_cache: Move code for triggering memory training into mrc_cacheShelley Chen
2020-11-13nb/intel/haswell/acpi: Do not add PEG devices for LPAngel Pons
2020-11-13nb/intel/haswell/acpi: Move PEG and CTDP includes downwardsAngel Pons
2020-11-13nb/intel/haswell/acpi: Merge `haswell.asl` into `hostbridge.asl`Angel Pons
2020-11-13nb/intel/haswell/acpi/hostbridge.asl: Drop unused registersAngel Pons
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