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2020-09-21nb/intel/ironlake: Clean up cosmetics of early ME functionsAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Ic766345b58c59f3d3c3570741c0eb0ad4e53ed79 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-21nb/intel/ironlake: Clean up `send_heci_uma_message` signatureAngel Pons
The only raminfo field it needs is `memory_reserved_for_heci_mb`. So, pass in that value directly. As it's read-only, make it const as well. Change-Id: Ib5d4604e6c1c9bc77df9adfead93b6028d536a3d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45365 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21nb/intel/ironlake: Reduce the scope of `heci_uma_addr`Angel Pons
There's no need to have it in raminfo. Also, bump MRC_CACHE_VERSION. Change-Id: Ida48ec4f50c880fe48d88d016acd3737a0650f80 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45364 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21nb/intel/sandybridge: Drop unnecessary `gma.h`Angel Pons
It only contains prototypes for the long-gone native graphics init. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I9413abb8e49496ada60dcdf801a1f8a03be38d2e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45360 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21nb/intel/sandybridge: Put DMIBAR/EPBAR registers into separate filesAngel Pons
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I836df4675f4886635973c0c75f5981c9ef17d84b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45359 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21nb/intel/sandybridge: Move register headers into a subfolderAngel Pons
Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: Ie525e755f32599db97af7969fc7fbb36a5d826b6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45358 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21nb/intel/sandybridge: Clean up DMIBAR/EPBAR registersAngel Pons
Several registers have been copy-pasted from i945 and do not exist on Sandy Bridge. Moreover, other register definitions were missing. Use the newly-added definitions in existing code, in place of numerical offsets. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I9ad849f57bc68256a2a87ffdc856c4b521e35892 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45357 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21nb/intel/sandybridge: Introduce memmap.hAngel Pons
Move all memory map definitions into a separate header. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I7f2ff2a5cee8bf12e5dca74ff9f0b1a44e26cded Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45356 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/haswell: Put DMIBAR/EPBAR registers into separate filesAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ib68d8b88b0d79cb33d42f9e21cfb0e57abae75e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45355 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/haswell: Move register headers into a subfolderAngel Pons
Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I143b3c829be44a39e14902255cd4bb13bf02f0c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45354 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/x4x: Clean up TPM-related codeAngel Pons
Perform the read to the TPM base address using <arch/mmio.h> functions. Remove dead variable assignment and rename TPM base address macro. Tested with BUILD_TIMELESS=1. Asus P5QL PRO remains identical. Change-Id: I11d737903c57fce768b760fe717564dae8879ad0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-09-17nb/intel/pineview: Guard DMIBAR/EPBAR macro parametersAngel Pons
Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: I347466f56d3d5fb3793b3a25e4a825c844e50d42 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17nb/intel/pineview/iomap.h: Rename to memmap.hAngel Pons
It primarily contains definitions for MMIO windows. Change-Id: I8cd639c8c7d400a5bfd73735113dd27dd6f948e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17nb/intel/ironlake: Do not re-read ME UMA sizeAngel Pons
It has been read twice already, so don't read it a third time. Change-Id: I56ec3a10246f6ebe8074e7b8c164bda6b90eee87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17nb/intel/ironlake: Drop some unused function parametersAngel Pons
Some of the HECI functions do not need raminfo at all. Change-Id: If0720fa87e5e18820db77a1b61bcdb42ecc538fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17nb/intel/ironlake: Drop `heci_bar` field from raminitAngel Pons
This field is only written to, never read. Drop it from raminfo. Also, bump MRC_CACHE_VERSION as the saved data layout has changed. Change-Id: I83d6e69addff996e2f18472d3e1d4f7b9ba974fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-17nb/intel/haswell: Clean up register definitionsAngel Pons
Several registers have been copy-pasted from i945 and do not exist on Haswell. Moreover, other register definitions were missing. Although most of them are unused, native platform init may eventually use them. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I6b3a47b2af406da6b030d417f14a2f4d394aa9c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45353 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/haswell: Guard DMIBAR/EPBAR macro parametersAngel Pons
Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I5e1a02ba2ebf468f0d80b7f1838766280b6b7b22 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45352 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/haswell: Introduce memmap.hAngel Pons
Move all memory map definitions into a separate header. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ib275f9ad8ca9ff343604c9e8cbb130c74ddad54f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45351 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/sandybridge: Drop `void *` cast in `MCHBAR32`Angel Pons
This changes the binary for the native raminit code path. Tested on Asus P8Z77-V LX2, still boots with native raminit. Change-Id: Ie8f1205a64e5264cb909d67c1dd402c18a6241ad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45350 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
This allows us to drop some casts to uintptr_t around the tree. The MCHBAR32 macro still needs a cast to preserve reproducibility. Only the native raminit path needs the cast, the MRC path does not. Tested with BUILD_TIMELESS=1, these boards remain identical: - Lenovo ThinkPad X230 - Dell OptiPlex 9010 - Roda RW11 (with MRC raminit) Change-Id: I8ca1c35e2c1f1b4f0d83bd7bb080b8667dbe3cb3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45349 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/sandybridge: Drop invalid `DEFAULT_RCBABASE` macroAngel Pons
RCBA is located in the PCH. Replace all instances with the already-defined `DEFAULT_RCBA` macro, which is equivalent. Change-Id: I4b92737820b126d32da09b69e09675464aa22e31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45348 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17nb/intel/ironlake: Drop invalid `DEFAULT_RCBABASE` macroAngel Pons
This macro is unused, and RCBA is located in the PCH. Drop it. Change-Id: Id7c095496360bbe96dc2a36dcc557a1481c02c31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45347 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-15nb/intel/ironlake/raminit: Work around compiler bugPatrick Rudolph
This fixes commit e1d1fe454cf27d6b1c2ef5625f1cefc1a9c6ec9d initialize 'reply.command'. The compiler now optimized away the final condition, that checks the result of heci message, resulting in a binary that always calls die(). Fix that behaviour by using volatile. Tested on Lenovo T410: Boots again into Linux. Change-Id: I63cffc8812bd22695c01bf57283ca593b12e3d87 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-14nb/intel/ironlake: Reserve gap betwen TSEG and BGSMNico Huber
There may be a gap between TSEG and the graphics stolen memory due to the alignment done in `raminit.c`. If we allocate MMIO resources in this range, it misbehaves unpredictably, so reserve it. TEST=Booted Thinkpad X201s, allocated resources are above TOLUD. Change-Id: If305e9751ebf4edc945cf038ed72698f3696e52d Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45325 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14nb/intel/ironlake: Use an `index` variable for resourcesNico Huber
Change-Id: Ic587231b57c51db592c1647de138a67c55161e58 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-08nb/intel/ironlake: Use an enum for `gpu_panel_port_select`Angel Pons
The PRM does not describe the relevant bits, but Linux's i915 driver handles these bits the same way for both Ironlake and Sandy Bridge. Change-Id: Ice7412e335752bd7e297ad50f685effcefbd41d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08nb/intel/sandybridge: Use an enum for `gpu_panel_port_select`Angel Pons
All boards currently have backlight on either LVDS or eDP. Change-Id: I878bc7f1ff75a2b82b9556e855aff1d4d03e0268 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-08nb/intel/haswell: Drop `gpu_panel_port_select`Angel Pons
The corresponding bits in PP_ON_DELAYS are reserved MBZ. Change-Id: Icd2554c928a5908dfb354b81d3e6c5b5f242f1d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
BOOTBLOCK_CONSOLE is already set to yes in console/Kconfig file. Change-Id: I2a4ee517795bc7b378afc5eae92e2799ad36111b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-09-02{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)Elyes HAOUAS
Change-Id: I049441dd9074659effc1092dce08224974d60a2c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-31nb/intel/sandybridge: Add ECC error injection register informationAngel Pons
Change-Id: I669a611e804d67bb6e87775d273dc24b03b06691 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44396 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mrc_cache: Add mrc_cache fetch functions to support non-x86 platformsShelley Chen
Create two new functions to fetch mrc_cache data (replacing mrc_cache_get_current): - mrc_cache_load_current: fetches the mrc_cache data and drops it into the given buffer. This is useful for ARM platforms where the mmap operation is very expensive. - mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a given buffer. This is useful for platforms where the mmap operation is a no-op (like x86 platforms). As the name mentions, we are not freeing the memory that we allocated with the mmap, so it is the caller's responsibility to do so. Additionally, we are replacing mrc_cache_latest with mrc_cache_get_latest_slot_info, which does not check the validity of the data when retrieving the current mrc_cache slot. This allows the caller some flexibility in deciding where they want the mrc_cache data stored (either in an mmaped region or at a given address). BUG=b:150502246 BRANCH=None TEST=Testing on a nami (x86) device: reboot from ec console. Make sure memory training happens. reboot from ec console. Make sure that we don't do training again. Signed-off-by: Shelley Chen <shchen@google.com> Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24nb/amd/agesa: define DDR3_SPD_SIZE as a common valueMike Banon
Move a size of DDR3 SPD memory (always 256 bytes) to a common define. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
Change-Id: I6afea5c102299e570378a1656d3dcd329a373399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17nb/amd/agesa: read 256 bytes to SPD buffer instead of 128Mike Banon
Required for adding the XMP profiles support. SPD buffer is already 256 bytes at AMD AGESA vendorcode, so this is fine. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I7340b110477a4cc1ecb1c239181436e51952568f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40484 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17src: Use PCI_BASE_ADDRESS_* macros instead of magic numbersElyes HAOUAS
Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44371 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17nb/intel/x4x/raminit_ddr23.c: Remove dead assignmentElyes HAOUAS
Change-Id: I2da586abf63517a2e9b73ea4d3fab513370947bd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44292 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12nb/intel/sandybridge: Add comments to `struct iosav_ssq`Angel Pons
Add the ranges of bitfields as comments on the struct. Change-Id: Ib20a233806bfbdc9a81a77f4ef10f67a3cd2dc0e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner
2020-08-11nb/intel/sandybridge/raminit: Add commentsPatrick Rudolph
Add comments found when testing ECC scrubbing code. This is a cosmetic change. Change-Id: I7975f6070c2002930eec407a6b101a1295495b25 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40947 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11nb/intel/sandybridge/raminit: Fix ECC scrubPatrick Rudolph
The scrubbing method was never correct nor tested. Fix that by observations made on mrc.bin. Tested on HP Z220 with ECC memory and Xeon E3 CPU: The whole memory is now scrubbed. Change-Id: Ia9fcc236fbf73f51fe944c6dda5d22ba9d334ec7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40721 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-11nb/intel/sandybridge/raminit: Add ECC debug codePatrick Rudolph
* Add ECC test code when DEBUG_RAM_SETUP is enabled * Move ECC scrubbing after set_scrambling_seed() to be able to observe what has been cleared in the test routine. If clearing happens before set_scrambling_seed the data is XORed with a different PRN. Data read from memory will look random instead of all zeros. * ECC scrubbing must happen after dram_dimm_set_mapping() The ECC logic is set to "normal mode" in dram_dimm_set_mapping(). In normal mode the ECC bits are calculated and stored on write transactions. * Move method out of try_init_dram_ddr3(). This satisfies point 2 and point 3 of the list above. Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-06nb/intel/sandybridge: Drop inexistent device from DMARAngel Pons
There's no `function 1` on the iGPU device for this northbridge. Change-Id: I597446f703165447c3a0d0c1536583b08bc8450c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-06nb/intel/sandybridge: Deduplicate PCIEXBAR decodingAngel Pons
We can use `decode_pcie_bar` instead, as other northbridges do. Change-Id: I35bede573ef2635c54123f9e553003577ecd0ea7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-06nb/intel/sandybridge: Refactor `get_pcie_bar`Angel Pons
Turn it into `decode_pcie_bar`, taken from gm45. Change-Id: Id1c2cfbcac1a798d046beced790930511dc97972 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44121 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05{nb,soc}/intel: Use get_current_microcode_rev() for ucode versionSubrata Banik
This patch removes all redundant read microcode version implementation from SoC directory and refer from cpu/intel/microcode/microcode.c file. TEST=Able to get correct microcode version. Change-Id: Icb905b18d85f1c5b68fac6905f3c65e95bffa2da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44175 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05src: Use space after 'if', 'for'Elyes HAOUAS
Change-Id: I5d3a5ede47aefc7cc2ee330f8a0bcded16138764 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44173 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05src: Use space after switch, whileElyes HAOUAS
Change-Id: I150591aa3624895c4c321101a251547dd23d1db5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44172 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04nb/intel/x4x: Define and use `HOST_BRIDGE` macroAngel Pons
Other Intel northbridges do this. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change Change-Id: I50785b7bf3e3cc0eade7fda4b4b2e2bb71a54c31 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDsAngel Pons
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says: BIOS implementations must report these remapping structure types in numerical order. i.e., All remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. So, update the corresponding code to adhere to the specification. Change-Id: I1f84cae41c6281e0d545669f1e7de5cab0d9f9c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-04nb/intel/x4x: Remove dead assignmentsAngel Pons
The call to `decode_pcie_bar` always initializes these values. Change-Id: Iffdb2fc846a6fc1a1abc504370b6283e292b61c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/x4x: Refactor `decode_pcie_bar`Angel Pons
Constify and eliminate local variables where possible to ease reading. Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change. Change-Id: I6d2937146a4764823cfc45c69a09f734b2525860 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decodingAngel Pons
Other northbridges have a `decode_pcie_bar` function. Since it's not needed anywhere else, keep it as a static function for now. Change-Id: Ide42ffcebb73c3e683e0ccaf0ab3aeae805d1123 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/i945: Deduplicate PCIEXBAR decodingAngel Pons
We can use `decode_pcie_bar` instead, if we make it non-static. Change-Id: Ic39f3df0293b4d44f031515b1f868e0bb9f750c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/i945: Refactor `get_pcie_bar`Angel Pons
Turn it into `decode_pcie_bar`, taken from gm45. Change-Id: I81a398535f18ced10b5521bddcf21f3568e1d854 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/haswell: Use ASL 2.0 syntaxAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I9c69028ff13efa6999b6110fbcd9233a09def991 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-08-04nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntaxAngel Pons
This brings Ironlake closer to Sandy Bridge. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: Idde75e7295f642f8add34168bffe5851ea02fbc6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43687 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04nb/intel/sandybridge: Update to ASL 2.0 syntaxAngel Pons
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: Ie3570cd0a75c6b34581b35165c1c6393214ad0bb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-08-04nb/intel/x4x: Change signature of `decode_pciebar`Angel Pons
Rename it and make it return an int, like other northbridges do. Change-Id: I8bbf28350976547c83e039731d316e0911197d54 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons
Add `decode_pcie_bar` for consistency with other Intel northbridges. Change-Id: If04ca3467bb067b28605a3acccb8bda325735999 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/pineview: Refactor `decode_pcie_bar`Angel Pons
Constify and eliminate local variables where possible to ease reading. Tested with BUILD_TIMELESS, Foxconn D41S remains identical. Change-Id: Iaad759886a8f5ac07aabdea8ab1c6d1aa7020dfc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/pineview: Change signature of `decode_pciebar`Angel Pons
Rename it and make it return an int, like other northbridges do. Change-Id: Id526ff893320a77e96767ec642c196c2196f84e1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/pineview: Use `MiB` definitionAngel Pons
Also constify a local variable while we're at it. Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: I90ab35932d7c0ba99ca16732b9616f3a15d972dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/pineview: Remove dead assignmentsAngel Pons
The call to `decode_pciebar` always initializes these values. Change-Id: Ide45e1e5e8b8d6cfebd2fc4e272b1971b0a9b346 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/gm45: Deduplicate PCIEXBAR decodingAngel Pons
We can use `decode_pcie_bar` instead, if we make it non-static. Change-Id: I4d005290355e30e6fdaae3e8e092891fddfbe4fc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-04nb/intel/gm45/northbridge.c: Use `MiB` definitionAngel Pons
Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Ibfa9a6fa7818d0bd79d2c0d9331c0ca38a2b7fe3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-08-04nb/intel/gm45: Use PCI bitwise opsAngel Pons
While we are at it, also reflow a few lines that fit in 96 characters. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Icaca44280acdba099a5e13c5fd91d82c3e002bae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42189 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04nb/intel/i440bx: Make ROM area unavailable for MMIOKeith Hui
Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03nb/intel/ironlake: Add Generic Non-Core register definitionsAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Add Generic Non-Core PCI device definitionAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Add QPI Physical Layer registersAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I44db564c757647f493e92d35602178ef8b722517 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Add QPI Physical Layer device definitionAngel Pons
Like the QPI Link device, there can be more of these devices on multi-socket platforms. So, name it Physical Layer 0. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Ia5f6e42a742bc69237de38f1833e56c8da7c4f7e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Add QPI Link register definitionsAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: Id226a2fdcbd0fe48822c4f65746e14fb00db6b2e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Add definition for QPI Link PCI deviceAngel Pons
On multi-socket platforms, there can be two QPI buses, each with its own PCI device. We only have one QPI link on Arrandale, though. In case support for multi-socket processors ever gets added, name it Link 0. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Add SAD DRAM register definitionsAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Correct PCIEXBAR definitionAngel Pons
This register resides within the SAD's config space, and is 64-bit. Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Add definition for SAD PCI deviceAngel Pons
Let's hope this cheers up the poor System Address Decoder device. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Drop `D0F0_` prefix from register namesAngel Pons
Only some registers have such a prefix. Drop it for consistency. Change-Id: I1ef7307d10a06db8f3c1a05bd9184f21fceb9d90 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Rename memory map variablesAngel Pons
Uppercase variable names can be confused with register definitions. Use lowercase names instead, conforming to the coding style guidelines. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I61a28bf964ea8c2c662539825ae9f2c88348bdba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake/raminit.c: Drop unused defineAngel Pons
This is the only instance of `BETTER_MEMORY_MAP` in the tree. Change-Id: I118e5b5a0f10da56e2335828477caed81c5bf855 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake/hostbridge_regs: Drop D0F0_PMBASEAngel Pons
This register does not seem to exist on Ironlake. Change-Id: I3fba6a3fd443f2c9eab874e1d1b8f081f58b1536 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake/hostbridge_regs.h: Clean up registersAngel Pons
Remove duplicated definitios and sort them by ascending offsets. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: Idcfa64a39c12a4ac06a342ef9b51a01b806d4c84 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/ironlake: Put host bridge registers into its own fileAngel Pons
Looks like some registers are defined twice. Also, group some QPI registers together. They were scattered around and mixed with the host bridge registers, probably because other northbridges have such registers in the host bridge's PCI config space. But not Ironlake. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I6e60f7fcb1467f302618eeab1b0d995920a98569 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/pineview/hostbridge_regs.h: Clean up registersAngel Pons
Sort them by ascending offsets. Tested with BUILD_TIMELESS=1, Foxconn D41S does not change. Change-Id: I521aa3e49b17a9fb6b279ae758801356e510d054 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/pineview: Put host bridge registers into its own fileAngel Pons
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: I12d6adb8f130599a33d71d7c9f71914ee7c9e8ef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/x4x/hostbridge_regs.h: Clean up registersAngel Pons
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I8d68a1dd49769ac49009a8e628f7994bf461a05f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/x4x: Put host bridge registers into its own fileAngel Pons
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I2c59099f6ff0e9162c700c888fb8fbb3906b65e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-03nb/intel/haswell: Add Crystal Well PCI IDsIru Cai
From a log of a machine using Crystal Well CPU [1], Crystal Well CPUs use some new PCI IDs. Without this patch, the Crystal Well northbridge cannot be initialized in ramstage, thus the machine cannot boot. Some PCI IDs of Crystal Well related devices can be found in the PCI ID database [2]. Tested with i5-4570R (with LGA1150 mod) on ASRock H81M-HDS. The board boots to SeaBIOS with boot screen displayed on HDMI output, and then boots Arch Linux on a USB disk. [1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/DNHLQTNTRQT43T67DG7L2HVI5CV74ZCM/ [2] https://pci-ids.ucw.cz/read/PC/8086 Change-Id: Icfe55323fd06187148c788ebfa7b679b6944e4f3 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41658 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-31nb/intel/haswell: Configure VCs on Egress PortAngel Pons
System BIOS needs to program the Virtual Channel configuration. Change-Id: Ic8ff17b3a1c4414633a658c60f2c4f7b195e5825 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43821 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30nb/intel/x4x/rcven.c: Rename memory barrier functionAngel Pons
Use the name of the assembly instruction it uses, mfence. Change-Id: I98d7926434694a41fb6415bed4276741fa7996af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-30nb/intel/*: Fill in SMBIOS type 16 on SNB/HSWPatrick Rudolph
Fill in the maximum DRAM capacity and slot count read from CAPID0_A registers on Sandy Bridge and Haswell. While the register isn't part of the Core Series datasheet, it can be found in the corresponding "Intel Open Source Graphics Programmer's Reference" datasheets. Note that the values for DDRSZ (maximum allowed memory size per channel) need to be halved when only one DIMM per channel is supported. On mobile platforms, all but quad-core processors are subject to this restriction. Tested on Lenovo X230: On Linux, verify that `dmidecode -t 16` reports the actual maximum capacity (16 GiB) instead of the currently-installed capacity (4 GiB) or the max capacity assuming two DIMMs per channel is possible (32 GiB). Change-Id: I6e2346de1ffe52e8685276acbdbf25755f4cc162 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-28nb/intel/i945/gma.c: Remove extra indentationElyes HAOUAS
Change-Id: If48cd055477011cece7921cea462aab176e170fb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-28nb/intel/haswell: Enable DMI ASPMAngel Pons
On Haswell platforms, the processor and the PCH are two separate dies, and communicate through a high-speed bus. This is DMI (Direct Media Interface) on traditional two-package platforms, but single-package Haswell LP variants use OPI (On-Package Interconnect) instead. Since OPI is not routed through the mainboard, most link parameters are static and cannot be changed. OPI self-initializes on boot, anyway. However, DMI needs to be initialized in firmware. On Haswell, the MRC initializes the physical DMI link, but things like topology and power management need to be configured as well. And we don't do that properly. We enable ASPM on the PCH side of the DMI link, but not on the SA side. Both sides need to use the same settings, so enable DMI ASPM on the SA. Clearing the error status bits needs to be done on all Haswell variants. Tested on Asrock B85M Pro4, still boots. Change-Id: Ie97ff56eec9f928cfd2d5d43a287f3e0d2fbf3cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-26nb/amd/pi/00730F01/northbridge.c: Add include <types.h>Elyes HAOUAS
BIT(x) needs <types.h>. Change-Id: I20526f20d9528dd1fce20bcae933e04aea3d24f9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
The Kconfig lint tool checks for cases of the code using BOOL type Kconfig options directly instead of with CONFIG() and will print out warnings about it. It gets confused by these references in comments and strings. To fix it so that it can find the real issues, just update these as we would with real issues. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26nb/intel/haswell: Use macro for dimm->bus_widthElyes HAOUAS
Change-Id: Ice91a20470c107f7db0ac83301488ae5afed5a8b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26nb/intel/sandybridge: Add missing includesElyes HAOUAS
Change-Id: I9d54d0923a595734a84256ddcafb9dae17615cb0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43348 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25nb/intel/ironlake/raminit.c: initialize 'reply.command'Elyes HAOUAS
This to silent a bug found using gcc-10. src/northbridge/intel/ironlake/raminit.c: In function 'setup_heci_uma': src/northbridge/intel/ironlake/raminit.c:1805:11: error: 'reply.command' may be used uninitialized in this function [-Werror=maybe-uninitialized] 1805 | if (reply.command != (MKHI_SET_UMA | (1 << 7))) | ~~~~~^~~~~~~~ cc1: all warnings being treated as errors Change-Id: I0d13de549b6d428ac3675ee3f91eb5e42aeb25e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42461 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25nb/intel/haswell/hostbridge_regs.h: Clean up registersAngel Pons
Add missing registers and sort them by ascending offsets. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I98f836668144032d920b56afff878acc0a58ed82 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-24nb/intel/sandybridge: Put host bridge registers into its own fileAngel Pons
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: Ibfaecd6ab94d2caae9804bb827ce8e48a2166d35 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 05:32:52 +0000