summaryrefslogtreecommitdiff
path: root/src/northbridge
AgeCommit message (Expand)Author
2020-09-22nb/intel/ironlake: Use DMIBAR/EPBAR macrosAngel Pons
2020-09-21src/northbridge: Drop unneeded empty linesElyes HAOUAS
2020-09-21nb/intel/sandybridge: Check ME status only onceAngel Pons
2020-09-21nb/intel/sandybridge: Simplify SPD validity checkAngel Pons
2020-09-21nb/intel/ironlake: Clean up cosmetics of early ME functionsAngel Pons
2020-09-21nb/intel/ironlake: Clean up `send_heci_uma_message` signatureAngel Pons
2020-09-21nb/intel/ironlake: Reduce the scope of `heci_uma_addr`Angel Pons
2020-09-21nb/intel/sandybridge: Drop unnecessary `gma.h`Angel Pons
2020-09-21nb/intel/sandybridge: Put DMIBAR/EPBAR registers into separate filesAngel Pons
2020-09-21nb/intel/sandybridge: Move register headers into a subfolderAngel Pons
2020-09-21nb/intel/sandybridge: Clean up DMIBAR/EPBAR registersAngel Pons
2020-09-21nb/intel/sandybridge: Introduce memmap.hAngel Pons
2020-09-17nb/intel/haswell: Put DMIBAR/EPBAR registers into separate filesAngel Pons
2020-09-17nb/intel/haswell: Move register headers into a subfolderAngel Pons
2020-09-17nb/intel/x4x: Clean up TPM-related codeAngel Pons
2020-09-17nb/intel/pineview: Guard DMIBAR/EPBAR macro parametersAngel Pons
2020-09-17nb/intel/pineview/iomap.h: Rename to memmap.hAngel Pons
2020-09-17nb/intel/ironlake: Do not re-read ME UMA sizeAngel Pons
2020-09-17nb/intel/ironlake: Drop some unused function parametersAngel Pons
2020-09-17nb/intel/ironlake: Drop `heci_bar` field from raminitAngel Pons
2020-09-17nb/intel/haswell: Clean up register definitionsAngel Pons
2020-09-17nb/intel/haswell: Guard DMIBAR/EPBAR macro parametersAngel Pons
2020-09-17nb/intel/haswell: Introduce memmap.hAngel Pons
2020-09-17nb/intel/sandybridge: Drop `void *` cast in `MCHBAR32`Angel Pons
2020-09-17nb/intel/sandybridge: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
2020-09-17nb/intel/sandybridge: Drop invalid `DEFAULT_RCBABASE` macroAngel Pons
2020-09-17nb/intel/ironlake: Drop invalid `DEFAULT_RCBABASE` macroAngel Pons
2020-09-15nb/intel/ironlake/raminit: Work around compiler bugPatrick Rudolph
2020-09-14nb/intel/ironlake: Reserve gap betwen TSEG and BGSMNico Huber
2020-09-14nb/intel/ironlake: Use an `index` variable for resourcesNico Huber
2020-09-08nb/intel/ironlake: Use an enum for `gpu_panel_port_select`Angel Pons
2020-09-08nb/intel/sandybridge: Use an enum for `gpu_panel_port_select`Angel Pons
2020-09-08nb/intel/haswell: Drop `gpu_panel_port_select`Angel Pons
2020-09-02src: Drop redundant 'select BOOTBLOCK_CONSOLE'Elyes HAOUAS
2020-09-02{nb,soc}/intel/{haswell,broadwell}/memmap.c: Use ALIGN_DOWN(x, a)Elyes HAOUAS
2020-08-31nb/intel/sandybridge: Add ECC error injection register informationAngel Pons
2020-08-24mrc_cache: Add mrc_cache fetch functions to support non-x86 platformsShelley Chen
2020-08-24nb/amd/agesa: define DDR3_SPD_SIZE as a common valueMike Banon
2020-08-18src: Remove unused 'include <delay.h>'Elyes HAOUAS
2020-08-17nb/amd/agesa: read 256 bytes to SPD buffer instead of 128Mike Banon
2020-08-17src: Use PCI_BASE_ADDRESS_* macros instead of magic numbersElyes HAOUAS
2020-08-17nb/intel/x4x/raminit_ddr23.c: Remove dead assignmentElyes HAOUAS
2020-08-12nb/intel/sandybridge: Add comments to `struct iosav_ssq`Angel Pons
2020-08-11nb/intel/sandybridge/raminit: Add commentsPatrick Rudolph
2020-08-11nb/intel/sandybridge/raminit: Fix ECC scrubPatrick Rudolph
2020-08-11nb/intel/sandybridge/raminit: Add ECC debug codePatrick Rudolph
2020-08-06nb/intel/sandybridge: Drop inexistent device from DMARAngel Pons
2020-08-06nb/intel/sandybridge: Deduplicate PCIEXBAR decodingAngel Pons
2020-08-06nb/intel/sandybridge: Refactor `get_pcie_bar`Angel Pons
2020-08-05{nb,soc}/intel: Use get_current_microcode_rev() for ucode versionSubrata Banik
2020-08-05src: Use space after 'if', 'for'Elyes HAOUAS
2020-08-05src: Use space after switch, whileElyes HAOUAS
2020-08-04nb/intel/x4x: Define and use `HOST_BRIDGE` macroAngel Pons
2020-08-04nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDsAngel Pons
2020-08-04nb/intel/x4x: Remove dead assignmentsAngel Pons
2020-08-04nb/intel/x4x: Refactor `decode_pcie_bar`Angel Pons
2020-08-04nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decodingAngel Pons
2020-08-04nb/intel/i945: Deduplicate PCIEXBAR decodingAngel Pons
2020-08-04nb/intel/i945: Refactor `get_pcie_bar`Angel Pons
2020-08-04nb/intel/haswell: Use ASL 2.0 syntaxAngel Pons
2020-08-04nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntaxAngel Pons
2020-08-04nb/intel/sandybridge: Update to ASL 2.0 syntaxAngel Pons
2020-08-04nb/intel/x4x: Change signature of `decode_pciebar`Angel Pons
2020-08-04nb/intel/haswell: Deduplicate PCIEXBAR decodingAngel Pons
2020-08-04nb/intel/pineview: Refactor `decode_pcie_bar`Angel Pons
2020-08-04nb/intel/pineview: Change signature of `decode_pciebar`Angel Pons
2020-08-04nb/intel/pineview: Use `MiB` definitionAngel Pons
2020-08-04nb/intel/pineview: Remove dead assignmentsAngel Pons
2020-08-04nb/intel/gm45: Deduplicate PCIEXBAR decodingAngel Pons
2020-08-04nb/intel/gm45/northbridge.c: Use `MiB` definitionAngel Pons
2020-08-04nb/intel/gm45: Use PCI bitwise opsAngel Pons
2020-08-04nb/intel/i440bx: Make ROM area unavailable for MMIOKeith Hui
2020-08-03nb/intel/ironlake: Add Generic Non-Core register definitionsAngel Pons
2020-08-03nb/intel/ironlake: Add Generic Non-Core PCI device definitionAngel Pons
2020-08-03nb/intel/ironlake: Add QPI Physical Layer registersAngel Pons
2020-08-03nb/intel/ironlake: Add QPI Physical Layer device definitionAngel Pons
2020-08-03nb/intel/ironlake: Add QPI Link register definitionsAngel Pons
2020-08-03nb/intel/ironlake: Add definition for QPI Link PCI deviceAngel Pons
2020-08-03nb/intel/ironlake: Add SAD DRAM register definitionsAngel Pons
2020-08-03nb/intel/ironlake: Correct PCIEXBAR definitionAngel Pons
2020-08-03nb/intel/ironlake: Add definition for SAD PCI deviceAngel Pons
2020-08-03nb/intel/ironlake: Drop `D0F0_` prefix from register namesAngel Pons
2020-08-03nb/intel/ironlake: Rename memory map variablesAngel Pons
2020-08-03nb/intel/ironlake/raminit.c: Drop unused defineAngel Pons
2020-08-03nb/intel/ironlake/hostbridge_regs: Drop D0F0_PMBASEAngel Pons
2020-08-03nb/intel/ironlake/hostbridge_regs.h: Clean up registersAngel Pons
2020-08-03nb/intel/ironlake: Put host bridge registers into its own fileAngel Pons
2020-08-03nb/intel/pineview/hostbridge_regs.h: Clean up registersAngel Pons
2020-08-03nb/intel/pineview: Put host bridge registers into its own fileAngel Pons
2020-08-03nb/intel/x4x/hostbridge_regs.h: Clean up registersAngel Pons
2020-08-03nb/intel/x4x: Put host bridge registers into its own fileAngel Pons
2020-08-03nb/intel/haswell: Add Crystal Well PCI IDsIru Cai
2020-07-31nb/intel/haswell: Configure VCs on Egress PortAngel Pons
2020-07-30nb/intel/x4x/rcven.c: Rename memory barrier functionAngel Pons
2020-07-30nb/intel/*: Fill in SMBIOS type 16 on SNB/HSWPatrick Rudolph
2020-07-28nb/intel/i945/gma.c: Remove extra indentationElyes HAOUAS
2020-07-28nb/intel/haswell: Enable DMI ASPMAngel Pons
2020-07-26nb/amd/pi/00730F01/northbridge.c: Add include <types.h>Elyes HAOUAS
2020-07-26src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth
2020-07-26nb/intel/haswell: Use macro for dimm->bus_widthElyes HAOUAS
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 07:04:22 +0000