summaryrefslogtreecommitdiff
path: root/src/northbridge
AgeCommit message (Expand)Author
2012-05-29Sandybridge: Remove remnants of FDT support from MRC cache codeStefan Reinauer
2012-05-29Sandybridge: Fix MRC cache calculationStefan Reinauer
2012-05-24cbtypes.h: Unify cbtypes.h used in AMD board's codeVikram Narayanan
2012-05-11Hook up MRC cache updateStefan Reinauer
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
2012-05-08Some more #if cleanupPatrick Georgi
2012-05-08Clean up #ifsPatrick Georgi
2012-05-03Add missing newline to printk in Sandybridge init codeStefan Reinauer
2012-05-02Make Intel i5000 specific options only appear on i5000 systemsStefan Reinauer
2012-05-02Strip quotes from Sandybridge MRC blobStefan Reinauer
2012-05-02Sandybridge: Display platform information earlyVadim Bendebury
2012-05-01Update Ivybridge GT power meter tablesDuncan Laurie
2012-05-01Update ivybridge graphics initializationDuncan Laurie
2012-05-01Only send ME Dram Init Done message on SandybridgeDuncan Laurie
2012-05-01Modify DMI init for IvyBridgeVincent Palatin
2012-05-01Fix Sandybridge/Ivybridge mainboards according to code reviewStefan Reinauer
2012-04-30Sandybridge: Temporarily disable MRC cache finding codeStefan Reinauer
2012-04-30Add default map_oprom_vendev() for AMD Family 14h processors.Martin Roth
2012-04-28Reverse Vendor ID & Device ID for map_oprom_vendev()Martin Roth
2012-04-27SMM: Add udelay on Sandybridge systemsStefan Reinauer
2012-04-21Intel e7505: build as separate object fileKyösti Mälkki
2012-04-21Intel e7505: enable ECC scrubbingKyösti Mälkki
2012-04-20Refactor some alignment handlingPatrick Georgi
2012-04-19Intel e7505: refactor onlyKyösti Mälkki
2012-04-17Intel e7505: handlers for undocumented registersKyösti Mälkki
2012-04-16S3 code in coreboot public folder.zbao
2012-04-12Unify IO APIC address specificationPatrick Georgi
2012-04-11Intel e7505: cleanupsKyösti Mälkki
2012-04-11Intel e7505: renames onlyKyösti Mälkki
2012-04-05amdfam10: add phenom II as known cpuBernhard Urban
2012-04-05Add support for Intel Sandybridge CPU (northbridge part)Stefan Reinauer
2012-03-27Add the support for RDC R8610 NorthbridgeRudolf Marek
2012-03-16Fix AMD Fam15 CBMEM allocationStefan Reinauer
2012-03-16Fix AMD Fam12 CBMEM allocationStefan Reinauer
2012-03-16Fix AMD Fam10 CBMEM allocationStefan Reinauer
2012-03-16AMD Agesa: delete no-op bootblock filesKyösti Mälkki
2012-03-16Rename AMD_AGESA to CPU_AMD_AGESAKyösti Mälkki
2012-03-16Fix AMD Agesa leaking KconfigKyösti Mälkki
2012-03-16Intel northbridge I945: Apply un-written naming rulesKyösti Mälkki
2012-03-16VIA southbridge K8T890: Apply un-written naming rulesKyösti Mälkki
2012-03-16Fix AMD Fam14 cbmen allocationMarc Jones
2012-03-15Clean up whitespace in fam14 northbridge.cMarc Jones
2012-03-07Move C labels to start-of-linePatrick Georgi
2012-03-02Fix ECC disable option for AMD Fam10 DDR2 and DDR3.Marc Jones
2012-02-17Avoid ../../.. paths in ASL filesPatrick Georgi
2012-02-17Rename i945 ACPI files to not carry an i945_ prefixPatrick Georgi
2012-02-17Remove whitespace.Patrick Georgi
2012-02-16AGESA F15: AGESA family15 model 00-0fh northbridge wrapperKerry Sheh
2012-02-16RD890: AMD RD890/SR56X0 CIMX wrapperKerry Sheh
2012-02-10Remove non-existent includeSven Schnelle
2012-02-10i5000: halt second BSPSven Schnelle
2012-02-02Add Intel i5000 Memory Controller HubSven Schnelle
2012-01-31northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig optionPeter Stuge
2012-01-26Make Geode GX2 VGA setup work.Nils Jacobs
2012-01-10i945: fix tsc udelay()Sven Schnelle
2012-01-07Update geode GX2 tree to match LX.Nils Jacobs
2012-01-05Clean up AMD Fam14 SSDTMarc Jones
2011-12-31White space and coding style fixes.Nils Jacobs
2011-12-14k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-xFlorian Zumbiehl
2011-12-02Change AMD vendorcode buildKyösti Mälkki
2011-11-23k8 raminit: fix bug, improve clock selection, add clock limit for sock754Florian Zumbiehl
2011-11-16fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminitFlorian Zumbiehl
2011-11-07Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26Florian Zumbiehl
2011-11-01remove trailing whitespaceStefan Reinauer
2011-10-31Add support for E7505 northbridge.Kyösti Mälkki
2011-10-28Clear improper use of CONFIG_CACHE_AS_RAMKyösti Mälkki
2011-10-28copy e7501 component to e7505Stefan Reinauer
2011-10-19I945: replace #if defined() by #ifSven Schnelle
2011-10-15AMD CPU and chipset fixes for compilation with gcc 4.6Stefan Reinauer
2011-10-15use acpi.h include instead of manually adding acpi_slp_type.Stefan Reinauer
2011-10-14Fix compilation of AMD GX2 northbridge code with gcc 4.6Stefan Reinauer
2011-10-14Fix compilation of VIA CN700 northbridge code with gcc 4.6Stefan Reinauer
2011-10-14fix compilation of intel/sch northbridge code with gcc 4.6Stefan Reinauer
2011-10-12amdk8: ASL include for K8 temperature sensor support in ACPIChristoph Grenz
2011-10-03TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platformsenok71
2011-09-24Add AMD Family 10h PH-E0 supportQingPei Wang
2011-09-14AMD F14 Northbridge updatesefdesign98
2011-09-09Replace while with do; while to avoid repetitionNoe Rubinstein
2011-09-09Report GSE chipset and warn if the code has been compiled for the wrong chipset.Stefan Reinauer
2011-09-07AMD F14 southbridge updateKerry She
2011-08-04northbridge/intel/i440bx: Registered SDRAM modules support and fixesKeith Hui
2011-07-22Update AMD SR5650 and SB700efdesign98
2011-07-18Add AMD Family 10 cpu support to northbridge folderefdesign98
2011-07-10ASRock E350M1: ACPI-related BSOD fixScott Duplichan
2011-07-09Fix memory size reporting on AMD family 14h systems for >= 4GBCristian Măgherușan-Stanciu
2011-06-30Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP andRudolf Marek
2011-06-28Addition of Family12/SB900 wrapper codeefdesign98
2011-06-22Move existing AMD Ffamily14 code to f14 folderefdesign98
2011-06-22Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign98
2011-06-15i945 GMA: restore tft brightness from cmosSven Schnelle
2011-06-15i82801gx: replace cafed00d/cafebabe by definesSven Schnelle
2011-06-03This patch sets max freq defaults for ddr2 and ddr3for fam10.Marc Jones
2011-05-15agesa_wrapper: Avoid repetitive Kconfig depends, trivialPeter Stuge
2011-05-15Cosmetic cleanup.Scott Duplichan
2011-05-151) Remove unused kconfig options.Scott Duplichan
2011-05-15Build device paths for AP cores so that coreboot will report them to the OS.Scott Duplichan
2011-05-15Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR.Scott Duplichan
2011-05-11Work around unclean CMOS handling for nowPatrick Georgi
2011-05-10Change read_option() to a macro that wraps some API uglynessPatrick Georgi
2011-04-21more ifdef -> if fixesStefan Reinauer
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 11:31:35 +0000