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- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I73549b23bd1bfd4009e6467a5bdfeef7de81a0cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76272
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib649943e13b9b319297c4be68b7039b760ebd820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic6f42053b5303151906360d8512b9d63dd297854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76249
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie585a66118c6bd1951bd004bbccbed0ee0ba9f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76248
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
- Don't have resources overlap
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ia8562660cf69d188b0cab4869aa3190f014dbfdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5c6dcbc8ed79b79ee097c7a14fe14ed87af33c2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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- Use newer functions and avoid the * / KiB dance
- Use existing functions for figuring out TSEG and UMA
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I502eeb39c05bd4d00b01976c96884636baf3030c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I61ae378867f8c0d9e86092ebe8deec53800c4717
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Iccaeb685ba66112b9e05ed72b57eb840543d7c6a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Iab582458a7dd87e10bf14fd34f15c592b600f706
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
src/commonlib/include/commonlib/console/post_codes.h;
myArray=`grep -e "^#define POSTCODE_" \
src/commonlib/include/commonlib/console/post_codes.h | \
grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
grep -r "POST_$splitstr" util/cbfstool | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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In soc/amd this function is unused so drop it and rename
_acpi_fill_ivrs_ioapic().
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic403fd84cb9cd5805fbc6f0c5a64cefbf4b0cd81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
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Replace the magic constants by using defines.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie558de02cd4f8914409639a74c54b57df3418ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75665
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is needed to support 9-series PCH-H (e.g. Z97) and Broadwell
non-ULT CPUs (for which more magic is required).
Tested on Asrock Z97 Extreme6: Boots, but ME has to be disabled so that
the system remains on after 30 seconds. Apparently, something Broadwell
MRC.bin does results in the ME being unhappy, as there is no such issue
when not using MRC.bin at all (native RAM init). S3 resume is working.
Change-Id: I7b33660099fa75c5ad46aeeda17b1215729f96c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Reformat the string, fix whitespace, add single-quote before
genitive `s`, and correct the GPU tool name `intel_reg`.
Change-Id: I277603063806927837867a454ae0875578228109
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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There is only a single place where we need the LVDS EDID string. Let's
call gm45_get_lvds_edid_str() right there. This simplifies the API and
helps to follow the execution flow.
The function is moved to avoid a forward declaration.
Change-Id: I86f3a88e6b661bcf60319edbe301e70304924727
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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This is how res2mmio() is supposed to be used and there was no other
use of the `mmio` variable left anyway.
Change-Id: Ifa4645bcc9ae971966587d9b67662b9dc8bae3d0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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The PCI resource should only be probed as part of the device
.init process. We can simply do that first and know that we
can use the global `gtt_res` from then on.
This simplifies the signature of gm45_get_lvds_edid_str(), and
makes changes to the API user (lenovo/x200) necessary.
Change-Id: I6c96f715abfa56dcb1cd89fde0fbaef3f1cb63ae
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Being a static function, compiler is already putting its contents
in sdram_initialize(), its only caller.
Change-Id: Ie74d2283ef672a267d6a0c66d94aa0610f36c4f1
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74033
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With RAM init debug messages enabled, debug messages take up a lot of
flash space in romstage, with many repeated verbiage. By breaking
them up and factoring out the common verbiage, made possible with
printk(BIOS_DEBUG, "%s", ...), compiler can help deduplicate things
and make the romstage smaller.
When building for asus/p2b-ls with CONFIG_DEBUG_RAM_SETUP, this patch
shrunk romstage by 152 bytes.
Change-Id: I66e39e7901efbeb5ab72494ac02fc4d5e687c3a3
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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i440BX datasheet says all memory errors reported during RAM init
should be ignored. Do as it says.
Change-Id: Iaf85fde813aa083ae62218a2df5aec303e3c9f8c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73952
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This hook is specifically for asus/p3b-f so its mainboard code has
a chance to put SPD away after RAM init completes. What it intends
to do is done when GPO gets programmed in ramstage (and it's safe
to do so), and no other board needs this hook, so drop it.
Change-Id: Ib7874b4d2b69fdaa5f3c5a3421a62a629c4154a4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Instead of having the maximum number of possible CPU objects defined in
the DSDT, dynamically generate the number of needed CPU devices in the
SSDT like it's done on all other x86 platforms in coreboot.
TEST=APU2 still boots and Linux doesn't show any ACPI errors with this
patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states".
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id6f057ad130a27b371722fa66ce0a982afc43c6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73073
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Instead of having binaryPI generate a PSTATE SSDT that uses \_PR_ as the
scope for the CPU objects and patching this SSDT in coreboot to use the
\_SB_ scope in patch_ssdt_processor_scope, request binaryPI to use the
\_SB_ scope instead by setting the late platform configuration option
ProcessorScopeInSb to true.
TEST=APU2 still boots and Linux doesn't show any ACPI errors with this
patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states".
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I411201b55cfee30ae41da4e6814679bdb49e9bf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73386
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Return 0xf from PCI0 _STA method so that bit 2 is set which indicates
that the device should be shown in the user interface. This ports commit
c259d7192806 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS")
back from Stoneyridge.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5e724292431be7f7c2a0b6678b426831e3c19154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74990
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I799f61d13f7ae3ea753869ded282c14ed566793a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add the missing 'b' to the 4gb so that get_top_of_mem_above_4gb is in
line with get_top_of_mem_below_4gb.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic9170372d8b0c27d7de3bd04d822c95e2015cb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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TEST=Timeless build for pcengines/apu2 results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If95eb9e5135de2b256d1f584afcedfd6e0cf8d8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Use get_top_of_mem_below_4gb and get_top_of_mem_above_4g instead of
open-coding the functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6332b051acf8d00ba6528360b18ea0d3c4dc30fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Rename amd_topmem and amd_topmem2 to get_top_of_mem_below_4gb and
get_top_of_mem_above_4g to make it clearer what those functions return.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic6e98d94c731af74aea0ce276a9a7e4867e3986f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have
special handling for the time being.
Change of aopen/dxplplusu is coupled with sb/intel/i82801dx.
Change of emulation/qemu-i440fx is coupled with intel/i82371eb.
For asus/p2b, this adds MADT LAPIC entries, even though platform
has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates
the MADT, including an entry for LAPIC address.
Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Read IOAPIC ID and number of interrupts from programmed registers.
Change-Id: Ic8ba395bc220fdb691118719f7b32dd7400931f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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There is no longer a relation between MAX_CPUS and IOAPIC IDs,
start the cleanup with new declarations.
Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I1a39f355733d10ecd43a1da541ab2e66ba13db15
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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It will cache decoded EDID string in a static array. If called more
than once, a pointer to the static array is directly returned, without
reading EDID again.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ibdbe4d76f9b59e7ae83b60cda042c2d1c39827ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74180
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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IF its first call is get_blc_pwm_freq_value(NULL), null dereference
will occur.
Now when the parameter is NULL, it will return the value of the static
blc_pwm_freq directly, so the original behavior is kept.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I32354aa0fe1a3ca725c2031f973ffad0bda81ad5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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There are two conditions within the config space dump code, one to
print offset, one at the end to put a newline. Tweak the printk
strings so the first conditioned printk does it all and move the
second printk out of the loop to the very end.
Change-Id: Ie9dc744406ba20412892df96720e88e24c3d52bc
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73887
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When encountering really incompatible memory configurations, post a
standard POST_RAM_FAILURE code when dying. Gone are the "HALT"
messages that no longer serve any good purpose, instead fatal messages
are edited to always end with "!" to make them stand out even with
loglevel prefix off.
Change-Id: Ie1b9e5a0415e4c64b1f4e935689263f62db012b2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Of the 13 mainboards that implement mainboard_should_reset_usb() hook,
all but one do the same: Stop MRC from resetting USB when resuming
from S3 suspend.
This hook turns out is only here to facilitate a USB reset workaround
on samsung/stumpy for an old ChromeOS kernel which is no longer needed.
Drop the workaround, the hook, and headers no longer used.
roda/rv11/early_init.c is left with no useful code after this patch,
so drop it entirely from both bootblock and romstage.
Change-Id: Ib3a5a00c0a6b1528e39435784919223d16b3914e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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UBSAN complains about "shift out of bounds", likely because integer
literals are signed by default and the result of the operation will
shift into the sign bit, yielding a negative value. However, as the
negative value is then casted to an unsigned type, it works anyway.
To make UBSAN happy, make sure the two troublesome integer literals
are unsigned so that there's no sign bit to shift into.
Tested on out-of-tree Asrock Z97 Extreme6, UBSAN now dies elsewhere.
Link: https://ticket.coreboot.org/issues/449
Change-Id: Iaf8710a5ae4e05d9f41f40f9e3617e155027800c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72806
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the existing IO_APIC2_ADDR definition instead of a magic value.
TEST=Timeless build results in identical image for pcengines/apu2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7ee039e23309fdae0d614bb1fb0610d82564bf3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Duplicated branches found using 'Wduplicated-branches' GCC flag.
Change-Id: I252ea6aefb6d6c85135e640ba8deaa118be38f5e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I5b7b1c218a0e8c8ba713b370622fbc37a1e57097
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Removing default on/off from mainboard devicetrees is left as a follow-up.
Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries.
This can restore s3 resume capability for Sandy Bridge platforms lost
after commit d165357ec37c ("sb,soc/intel: Use
register_new_ioapic_gsi0()").
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72513
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>.
Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the remaining DDR2 code to program the registers for memory
timings, ODT, RCOMP, and refresh mode; and perform receive-enable
calibration.
TEST: DDR2 systems boot
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: I6d9a1853fea9e29171d7c2f9ffe7086685c9efad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move DDR3 memory I/O init to its own function and add DDR2 memory I/O
init. Read I/O init is common to both DDR2 and DDR3.
TEST: DDR2 systems boot (with the rest of the patch train)
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: Ic4d5130f527249d3a5b98bae778cdf21a1753b04
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Split JEDEC init into common and DDR3 specific parts and add the DDR2
specific init code. This also replaces raw `mchbar_clrsetbits32` calls
with a dedicated `jedec_command` function.
TEST: DDR2 systems boot (with the rest of the patch train)
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: I7a57549887c0323e5babbf18f691183412a99ba9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34827
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add initial support for DDR2. This also changes GM45 raminit to
internally work in units of 1/256 ns for both DDR2 and DDR3 instead of
the 1/8 ns MTB assumed for DDR3, which simplifies the handling of time
values. DDR3 time values are thus scaled by a factor of 32 accordingly.
TODO:
- DDR2 JEDEC init
- Memory IO init
- Register programming
TEST: DDR2 systems boot (with the rest of the patch train)
- Tested on a Dell Latitude E6400
- Tested on a Compal JHL90
TEST: Ensure DDR3 systems still boot
- Tested on a Thinkpad X200
Change-Id: I265938d58c30264fd5d4f7b89da7b689058b8cf8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34826
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I93455f38663cf29d8b5160ac21c94db08eb44fa9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I885cc00c8bfcfaaabb2ce2b0269172d8d7a88db5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move specific enum ddr3_module_type to <device/dram/ddr3.h>.
Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Icecef272bd4cd2a204c903783787bbec751fe9e5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ib1bf132f248d1f3c42d32f884f09687964a0c6f2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Idda0a8330463205efe5ec5faa82a1f458894e521
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: If94037f2b010527440795e6920dd7a533c52f606
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I6af7131e151700569d50e8bc42bfaeb7a58fa7d3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71507
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I75bc048d9e04be8d0cab25f6aad1c71d3e7a4008
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71506
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1ff0132e17b08f492828eb13d66e167eae45250d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71505
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I059e94ef46fdc959a6e37365eb335409698b987a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Implement some scaffolding for Haswell native raminit, like bootmode
selection, handling of MRC cache and CPU detection.
Change-Id: Icd96649fa045ea7f0f32ae9bfe1e60498d93975b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Implement native PCH initialisation for Lynx Point. This is only needed
when MRC.bin is not used.
Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Implement native thermal initialisation for Lynx Point. This is only
needed when MRC.bin is not used.
Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64180
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implement native USB initialisation for Lynx Point. This is only needed
when MRC.bin is not used.
TO DO: Figure out how to deal with the FIXME's and TODO's lying around.
Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Implement native early ME init for Lynx Point. This is only needed when
MRC.bin is not used.
Change-Id: If416e2078f139f26b4742c564b70e018725bf003
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Implement native DMI init for Haswell and Lynx Point. This is only
needed on non-ULT platforms, and only when MRC.bin is not used.
TEST=Verify DMI initialises correctly on Asrock B85M Pro4.
Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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__ACPI__ is covered through __ASSEMBLER__.
Change-Id: I6a637e63c6bbe4af7cd52be1893e47d6b5967886
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70697
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Introduce the `USE_NATIVE_RAMINIT` Kconfig option, which should allow
booting coreboot on Haswell mainboards without the need of the closed
source MRC.bin. For now, this option does not work at all; the needed
magic will be implemented in subsequent commits. Add a config file to
make sure the newly-introduced option gets build-tested.
Change-Id: I46c77586f9b5771624082e07c60c205e578edd8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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<device/mmio.h>` chain-include `<arch/mmio.h>:
https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes
Also sort includes while on it.
Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ie2b1131d7db4b81bd6eb2df7a5ba8a6e8b54539b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ibbefa3d57b17a6a8eb0831eeadf6d629e2765567
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Ia974da56090b8f9de03c29cda62bc1fb9ef3a082
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I78337cf822cfae177b9ef3040641057a84e90e15
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I3bbb2f02a2dc182956deffc554a6b161a93ad963
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I0984ff1d0b1908bfb7028910f2c6f1083e153520
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.
This removes the need for a magic lapic in the devicetree.
Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I5f11bde99dfcde81c9dc62c1102330c0a6c16e04
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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'gpu_lvds_use_spread_spectrum_clock'is only used on i945.
Change-Id: I0f63f18d3f57ef8774f22ca9eb8c20dd39c56cdc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70147
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4a49f37e6fe0cb04c8112baf36fd8d01ab218045
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69293
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of using a fake lapic device hook up the cpu cluster to chip
cpu/intel/model_206ax.
The lapic device is also not needed as the mp init will allocate it for
the BSP at runtime.
Change-Id: Id3b1c4ca027e2905535e137691c3e3e60417dbf3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Also remove the now unnecessary comments from the devicetree.
Change-Id: Iebbe12fd413b7a2eb1078a579e194eba821ada7c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I718d9dbc184c8bca38f452efea3202901018cb04
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69291
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This only moves CPU configuration to a common place. Other PCI devices
can be done in follow-ups.
Change-Id: I9c5b6f25b779e28b6719cf70455ff0f1a916ad87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56912
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I70fb470b63ddd06f1d1e34deaea296d81e24f75f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70058
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Both SMM_ASEG and SMM_TSEG choices work.
There is periodic TCO timeout occurring.
At least with DEBUG_SMI kernel reports low memory corruption.
Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.
Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: If6c1a17d15e24ecdc56b0cc9cb7e7dc7d6e6936b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Get rid of a lot of casts.
Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Change-Id: Ife134ef6d508113e3cd27b6352ee5044aee43744
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I4baa2e06d336736caf5505a05ed4353bcbfdb517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: I713b3fed3fc6d55139badec93a67943dd93ced2a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69333
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Make the implementation more similar to i82801gx, enabling
ACPI PM and GPIO register spaces already in bootblock.
Change-Id: I41ad8622801dbbadafdc37359d521eed42256e63
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I9dd254eddc12966154776d8a2d43f002567e758f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69290
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's not clear whether this variable should actually be used or not so
leave it be with a FIXME comment.
Change-Id: I4892600bfec55830acae56d2b293947c2d9ddd07
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69237
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit eb76a455cd39ec59b7f2ba28baeec9538befd59e
and applies minor fixes to make it build again.
PARALLEL_MP was working prior to board removal and no
relevant SMI handlers were implemented. So NO_SMM choice
is now selected.
Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I955274bc6bda587201f130762c0735c36f5501d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69289
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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