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2018-06-17nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki
Boot tested on asus/p2b-ls and p2b-ds. Change-Id: I0154f1d120bef3b45286fb4314f0de419cd8341e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/26821 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-17nb/intel/i440bx: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: I96f42d5dc10d36855bdca64d1406a254250ee5b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26820 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-17cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki
This moves CAR stack under variable MTRRs and removes old CAR code that used complex fixed MTRRs and placed stack in low memory. Change-Id: I75ec842ae3b6771cc3f7ff652adbe386c03b9a5f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/26586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-17nb/intel/nehalem: Fix DEVEN definesPatrick Rudolph
The DEVEN defines are wrong, but weren't used at all. Fix them as they are needed by the hybrid_graphics_driver and use the defines instead of magic values. Tested on Lenovo T410: The IGD turns on with the correct value. Change-Id: Idf9fc0115de5c72f7d5d88cbb09ae1d2fee0afd0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-17nb/intel/x4x: Issue a hard reset with empty MRC cache on warm resetArthur Heymans
The dram controller cannot fully initialize the dram on warm reset (receive enable calibration consistently fails) therefore requiring cached timings. This option is mostly useful when rebooting after having flashed a new rom which overwrites the mrc cache region. Change-Id: I405c0eca076fe081641ede9a670f734c98cbf8fc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-14cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans
Tested on Google peppy (Acer C720). Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-14nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xceElyes HAOUAS
Change-Id: Ifb8aa43b6545482bc7fc136a90c4bbaa18d46089 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22957 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
Libgfxinit provides a better alternative to the native C init. While libgfxinit mandates an ada compiler, we want to encourage use of it since it is in much better shape and is actually maintained. This way libgfxinit also gets build-tested by Jenkins. Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
Some things were coding errors, other things need to be fsb specific. Most things here don't seem to matter all that much but better to get it right. Change-Id: I1afa637a16a083c3a945ba3e2a71292b005736fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14nb/intel/x4x: Work around a quirkArthur Heymans
It looks like this hardware has a bug where the display controller does not work properly when dram is clocked 533MHz and the channels are configured in non-stacked mode. The workaround is to select stacked mode in this configuration. Change-Id: I6f37ce15a4e98a4cdbd6d893f22846a65c8be021 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
There seems to be a hardware bug where the combination of non-stacked channel settings, both channels populated and 533MHz dram speed cause the display to be unusable. The code to actually select stacked mode based on hardware configuration will be add in a followup patch. This patch does the following: * Add option to the sysinfo struct for stacked mode * Fix programming channel 1 DRB which needs special care for the last populated rank in stacked mode TESTED on Intel dg41wv (with stacked mode hardcoded and dram at 533MHz) Change-Id: I95965bfea129b37f64163159fefa1c8f16331b62 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14src: Use of device_t is deprecatedElyes HAOUAS
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14AGESA binaryPI: Drop RAMBASE and RAMTOPKyösti Mälkki
With platforms moved to RELOCATABLE_RAMSTAGE, these overrides no longer have a meaning. Overrides existed because AGESA ramstage did not fit within the default 1 MiB of RAMTOP - RAMBASE, when placed low. Change-Id: I0185875dc550de74877c94f36128d5979e5553d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26813 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-11{src,util}: Use NULL instead of 0 for pointerElyes HAOUAS
Change-Id: I75fa4577055f25dde0a8b1044c005bba72cabd92 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
Change-Id: Ia637d32ffaa5d280320955d34141eddc8b7df981 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22222 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans
TSEG can be used as a stage cache and SMM can be relocated here. Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25593 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans
TSEG can be used as a stage cache and SMM can be relocated here. Tested on Intel D945GCLF, still boots. Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25592 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-07nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans
This adds a common function to decode the TSEG size from the ESMRAM register. This will come in handy when SMM in TSEG is implemented. This function is used both in romstage and in ramstage. Change-Id: I4e163598752fb6cd036aec229fce439ebad74def Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23448 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06intel/e7505: Remove ROMCC workaroundKyösti Mälkki
Choose codepath as if ROMCC_IF_BUG_FIXED was set. Change-Id: I74b4fe4a915b70f63ea018035381b64f53af3c7f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06arch/x86: Flag platforms without RELOCATABLE_RAMSTAGEKyösti Mälkki
To flip the Kconfig default, flag some platforms with NO_RELOCATABLE_RAMSTAGE. Change-Id: I72c6d07e5a60789bbe0e068a0130d7e3bd07a1d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-05northbridge/amd/lx: Fix function setShadowRCONFIru Cai
GCC 7.1 found an int-in-bool-context in northbridgeinit.c. The logical `&&` in `if (shadowByte && (1 << bit))` should be changed to bitwise `&`. Also fix off-by-one error with the bitmasks. Change-Id: I7d7720121d4730254542372282f5561739e7214b Signed-off-by: Iru Cai <mytbk920423@gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20808 Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05amd/geode_lx: Fix .c includesKyösti Mälkki
Change-Id: I2cce52561d30e30e1c81752cd2a455e7211006eb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2018-06-05cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans
Tested on Google Peppy (Acer C720). Change-Id: I1802547d7a5b3875689cc4e126e7c189a75defa9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26793 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05cpu/intel/model_2065x: Switch to POSTCAR_STAGEArthur Heymans
Also removes some non-POSTCAR_STAGE functions, since those are unused now. Change-Id: I439bffbe39411186355d374eed7d5efd63fb02e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26792 Reviewed-by: Matthias Gazzari <mail@qtux.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05cpu/intel/model_206ax: Switch to POSTCAR_STAGEArthur Heymans
Tested on Lenovo Thinkpad X220 with both native raminit and mrc.bin. Change-Id: I5e1a1175d79af4dc079a5a08a464eef08de0bcbf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05nb/intel/gm45: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: I02165cf63710bedcafe9287cbe8a1d1fe41ebae2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26788 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: Ib7f0009bf024d1f09483e0cfc696d234ec78d267 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05nb/intel/pineview: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: If23925e2837645c974e4094e7e2d90e700d3d9e8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-05nb/intel/i945: Switch to POSTCAR_STAGEArthur Heymans
Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04intel/i440bx: Drop tests for LATE_CBMEM_INITKyösti Mälkki
Change-Id: I08c28862cc66956bdcab6ac9362b3d50bb64e78f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Ib2bb6cc80ac2bdc389c60c7ffac4bba937f0fca8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04nb/intel: Use postcar_frame_add_romcache()Nico Huber
Change-Id: I0729ca4cdad7d2218c1e1feae5cd38dda6d4e11e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04nb/via/vx900: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I31143e1c7f1c52dec9673f75d73031632049ddbf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26529 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
Change-Id: Id299295784d6fcb04234b085566995bbd8a03d01 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-06-02intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGEKyösti Mälkki
Change-Id: Ie522e8fda1d6e80cc45c990ff19a5050165d8030 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-02intel/e7505: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: Icc4cef468ede2c1db052850efd155b626e392dae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26744 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-02intel/e7505: Assume AGP slot disabledKyösti Mälkki
Reducing two AGP aperture windows from default 256 MiB to chipset minimum 4 MiB releases 504 MiB of unused MMIO space. Thus we can decrease MMIO space reserve from 1024 MiB to 512 MiB. Supported CPUs are 32-bit with PAE, so there is a little reason to avoid overlarge MMIO region. Change-Id: I34818e1ca36058309c7c5c295992ba6dda154acc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INITKyösti Mälkki
With implementation of LATE_CBMEM_INIT, top-of-low-memory TOLM was adjusted late in ramstage. We do not allow that with EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO space is now used with statically set TOLM. Also remove support code for the obsolete LATE_CBMEM_INIT this northbridge used. Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-02intel/e7505: Fix domain resourcesKyösti Mälkki
Fixed resources have to be registered early during read_resources() phase, such that device allocator will avoid them. Change-Id: I3c120cfb96c185f0052b9b3cdd93eeed0f712491 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-31Remove VIA VX800 northbridge supportKyösti Mälkki
Change-Id: Id6026e9d7ff064d54b0dd93e80dabdcc4efd2b8e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31Remove VIA CX700 northbridge supportKyösti Mälkki
Change-Id: Id46e3d40393598f6b03ae4fd3186182635f072ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31Remove VIA CN700 northbridge supportKyösti Mälkki
Change-Id: I6c33d35718cc445ce67fc625d71420ded3828d8b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-31Remove AMD K8 cpu and northbridge supportKyösti Mälkki
Change-Id: I9c53dfa93bf906334f5c80e4525a1c27153656a3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-31Remove southbridges after K8 board removalsKyösti Mälkki
Change-Id: Ib6935c026e2302b037fc82be64163f10bf775751 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-31Remove all AMD K8 boardsKyösti Mälkki
Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-29src/northbridge: Add and update license headersMartin Roth
This change adds and updates headers in all of the northbridge files that had missing or unrecognized headers. After this goes in, we can turn on lint checking for headers in all northbridge directories. Change-Id: I8cd7c04ddb8e58946dcdf9c7c125e23698647a73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-05-24nb/intel/fsp_sandybridge: Fix lost const qualifier on 'device_t'Elyes HAOUAS
Missing '*const' in Change #26195 added into function northbridge_get_tseg_base(void). Change-Id: Ideb9a9cb98d34f2ed1034b8ee20b3b06aa5ff1e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26455 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24AMD geode/lx: Remove generic_sdram.c includeKyösti Mälkki
The file under lib/ will be removed with K8 and Geode LX is the only other platform using it. Change-Id: Id49d72358ecfc4aae4980e3ae787952073e5c838 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24Remove leftover AMD CIMX RD890 northbridge supportKyösti Mälkki
Change-Id: I3f2cea79a11a52e94f479b25f22eb3726af38fa3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-24nb/amd/amdfam10: Get rid of device_tKyösti Mälkki
Change-Id: Iac6be374842063cc383af20c73900e3699a72653 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
Change-Id: I9d34154d3ac1dd1e5400d692d4dcce70d95662c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans
When programming the final dram attribute and dram boundary settings, on DDR3 dram one also needs to enable ZQCAL in the CxREFRCTRL (DRAM Refresh Control) register as documented in "Intel ® 4 Series Chipset Family" documentation. Change-Id: I11a79f6800dbfe19c2bd33c0d6caca14b034e384 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
DDR3 adapted a fly-by topology which allows for better signal integrity but at the same time requires additional calibration. This is done by settings the targeted rank in write leveling mode while disabling output buffer on the other ranks. After that the DQS signal gets sampled over DQ until a transition from high to low is found. Change-Id: I695969868b4534f87dd1f37244fdfac891a417f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs) This also modifies the send_jedec_cmd function as DDR3 dimms can have ranks mirrored which needs to be accounted for. The ddr3_emrs1_config array is placed externally since it is also needed for write leveling. Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24nb/intel/sandybridge: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If36a879fbe7a93a214d74dbfa6fb3ee2d09a044a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-23nb/amd/pi: Get rid of device_tKyösti Mälkki
Change-Id: I9b1c597f5c6995f19e9697e8aa698fa672a220b1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26473 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23nb/amd/agesa: Get rid of device_tKyösti Mälkki
Change-Id: I5bd1c1cd71bd9541c1a95d444cd8d5ff40687dde Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26436 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-21nb/amd/amdk8: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If540a8b0afb93c1ba8e901c4771228a43c1e6a14 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-21nb/via/cx700: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Iaca908cc9ba5d11468a97d2f43911db925b93f1e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-21nb/via/vx800: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ib432d3c3ce2788b0138a1b0e852385ab4f9b65ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-21nb/via/cn700: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ic58bb58b88ffc309472ee9ffc8a9c8619659811b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-21nb/intel/nehalem: Fix smashed stack in romstageMatthias Gazzari
Stack smashing was detected during raminit when not loading from MRC. Adding CAR_GLOBAL to a struct inside raminit was suggested in https://mail.coreboot.org/pipermail/coreboot/2018-May/086677.html in order to fix the problem. Adding CAR_GLOBAL to the ram timings variable solves the issue (adding it to the ram_training or raminfo struct had no effect). This is just a workaround and might need a proper fix in the future. Tested on Lenovo X201i with 2+2 and 4+4 GB RAM. Change-Id: I21b380db61be2aedc045201821d83e18e7d07ad1 Signed-off-by: Matthias Gazzari <mail@qtux.eu> Reviewed-on: https://review.coreboot.org/26388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-20nb/amd/agesa/family14: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I9841fa591c4051653267b9e7c2f5b347d6f25b74 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-20nb/amd/agesa/family12: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I265130532965c1655c34fd7dab6ca9ef0e27beca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-19via/vx900: Remove leftover codeKyösti Mälkki
Code is not used with EARLY_CBMEM_INIT and it appears to have been invalid register anyways. Change-Id: If0662937b38aec71292113ce8abd88da0b73feee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-18nb/common/intel: Remove the mrc cache codeArthur Heymans
This is now unused, since all intel northbridges now use the equivalent in drivers/mrc_cache. Change-Id: I3e4b4afa53acc0a82b4ba961f13f816b04931fea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23485 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-18nb/intel/nehalem: Use the common mrc cache driverArthur Heymans
The common mrc cache driver allows to save the raminit training results to a separate fmap region which is more manageable than a cbfsfile. Change-Id: I25a6d3fe5466d142e3d10429a87b19047040c251 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-18nb/intel/e7505: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I2176ea83fac30052c02d9f6e98c89c40436a38e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-18nb/intel/haswell: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I10fb736a7406a6571dffce883fb82c2711526762 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-17nb/intel/nehalem: Add ACPI pathPatrick Rudolph
Provide a valid ACPI path for coreboot's SSDT generators. Fixes all ACPI errors found while booting GNU Linux 4.15 on Lenovo T410. Change-Id: Idd4986f39f21cb53cb019d0893d40fed94c6505b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/26287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-05-16vx900: Move to EARLY_CBMEM_INITLubomir Rintel
To calculate the CBMEM address we need to determine the framebuffer size early in the ROMSTAGE. We now do the calculation before cbmem_recovery() and configure the memory controller right away. If the calculation was done from cbmem_top() instead, we'd loose some logging that seems useful, since printk() would recurse to cbmem_top() too with CONSOLE_CBMEM enabled. If we didn't configure the memory controller at this point, we'd need to store the result somewhere else. However, CAR_GLOBAL is not practical at this point, because calling car_get_var() from cbmem_top() would recurse back to cbmem_top(). Change-Id: Ib9ae0f97f9f769a20a610f8d76f14165fb924042 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/25798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2018-05-14nb/intel/fsp_sandybridge: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Id3289c891e8a81c750fc3f5fad0fd16c0f2702fe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-14nb/intel/i945/raminit.c: Remove not necessary braces {}Elyes HAOUAS
Braces {} are not necessary for single statement blocks. Change-Id: I2a2d8672fe3f53450dcfa53dc127b89b4aa6b75e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19876 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
Change-Id: Ifef905f5115ffc826b1a355e54c4b1ca818e56fa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19875 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
Adapt the programming of initial DLL values for DDR3. Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans
Also throws in some minor fixes like the wrong conditional for bankmod and using real CAS when programming MCHBAR(0x248). Change-Id: Ia2494684ec66d84d4dc27c6a6b425a33ace6e827 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
Adds nmode to the sysinfo struct as it is needed later on. Change-Id: Ia2ca4a200a1c813b2133eb1004fbe248fa3de9ce Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19872 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans
A few values were wrong, but it does not seem to matter all that much. Change-Id: I86b70e06c81817854994b7feddf9f3638fd16198 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19871 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
This memory controller supports both DDR2 and DDR3 memory, yet many functions have ddr2 in their name while not being ddr2 specific. This patch renames those to avoid confusion. Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans
Since this memory controller supports both DDR2 and DDR3 allow it to decode both while making the dram type mutually exclusive. Change-Id: I8dba19ca1e6e6b0a03b56c8de9633f9c1a2eb7d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans
Some things in programming registers related to dual channel interleaved operation were wrong. This also adds some code that could in the future be used when me is active and claims some memory for its UMA. This also uses some more sensible variable names to clarify at least some of the magic. This fixes memtest86+ failing with some assymetric DIMM configuration. TESTED on DG43GT: memtest86+ now succeeds on many more different DIMM configuration setups (would instantly fail at addresses above 4G on many configurations). Change-Id: If84099d27100e57437bf214dc4cf975f67c2ea1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14agesa/family16kb/northbridge: report acpi namespaceKevin Cody-Little
Add a function domain_acpi_name to return "PCI0", rather than falling back to the parent' device's "\_SB" label. This repair is required for the LPC TPM device to register its presence without blowing up the table and preventing the payload from finding SATA. Before change, the TPM device reported as: \_SB.\_SB.LPC0.TPM After change, the TPM device reports as: \_SB.PCI0.LPC0.TPM A separate change submission will correct "LPC0" as well. Change-Id: I5e8d4715c9b42f50c84dd65818e4b0fdfc9d54f9 Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com> Reviewed-on: https://review.coreboot.org/26204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-11nb/intel/i945/bootblock.c: Correct commentElyes HAOUAS
Change-Id: Ic28ff80eb1dae6d0a307e2a1b73e8129fffbac13 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-11nb/intel/i440bx: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I69c8b95ff1937c0b08147d9e26a3118c58129cf5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-09{device,drivers,lib,mb,nb}: Use only one space after 'if'Elyes HAOUAS
Change-Id: I390191fb58605d1bd6a2e5d19a9dfa7c8493e6b2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04amd/mct/ddr3: Correctly configure CsMux67Patrick Georgi
The existing logic to set up CsMux67 used an incorrect mask and comparison value due to a copy + paste editing error. Use the correct mask and comparison value for the last two values. Commit cf1cb5b2d4f528e7eab55ee9393cf72016bac888 did the same for CsMux45 but missed this one. Change-Id: Ib97ca89535b8291397d42eca69e217c21a9dd937 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/25994 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01nb/intel/x4x: Change memory layout to improve MTRRArthur Heymans
This change also makes sure that the sum the uma regions (TSEG, GSM, GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between 2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR setup for ramstage. At least tianocore requires this and fails to boot without it. Better MTRR are achieved by making the memory 'hole' till 4GiB exactly 2Gib. This code mimics how it is done in nb/intel/gm45 and achieves similar results. TSEG is enabled and set to 8M since this makes it easier to reuse the common smm setup / parallel mp code and makes it possible to cache the ramstage in there like how it's done on newer targets. TESTED on Intel DG43GT. Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-01nb/intel/x4x: Fix programming CxDRBArthur Heymans
Programming CxDRB should be cumulative as explained in "Intel ® 4 Series Chipset Family datasheet". This does not seem to have any real impact but better do according to the documentation and what vendor firmware does. This also removes some dead code. Change-Id: I7ff3264824c843f84b9eb6c06a06aa3f151fe4b3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22911 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01nb/intel/x4x: Implement both read and write trainingArthur Heymans
This training find the optimal write DQ delay and read DQS delay settings. It does so on all lanes at the same time, like vendor (training each lane individually has poor results). The results are stored in the sysinfo struct and restored on next boots and S3 resume. This potentially increases stability as optimal settings are chosen and is more necessary for DDR3 raminit where the write DQS delays are leveled/variable due to the flyby topology. TESTED on Intel DG43GT with (2G + 1G) on each channel, see that the results are quite close to the safe original ones (that previous worked fine) and tested with memtest86+. Change-Id: Iacdc63b91b4705d1a80437314bfe55385ea5b6c1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-01Fix freeze during chipset lockdown on NehalemMatthias Gazzari
Remove locking of PCI device 00:00.0 registers (nehalem/finalize.c) and remove setting the zeroth bit of the MSR_LT_LOCK_MEMORY = 0x2e7 MSR register (model_2065x/finalize.c) to fix a frozen boot and S3 resume issue which became apparent with commit d533b16669a3bacb19b2824e6b4bc76a2a18c92a. More detailed, either setting the LSB of the 32 bit register at 0x98 of the PCI device 00:00.0 (in the intel_nehalem_finalize_smm function) or setting the LSB of the the MSR register MSR_LT_LOCK_MEMORY = 0x2e7 (in the intel_model_2065x_finalize_smm function) indepentenly causes a freeze during bootup or a complete session loss on resuming from S3 as described here: https://mail.coreboot.org/pipermail/coreboot/2018-April/086564.html It seems like Nehalem CPUs do not have a MSR_LT_LOCK_MEMORY register. Additionally, the "Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series, Datasheet Volume Two" indicates that registers of the PCI device 00:00.0 cannot be locked manually. Instead, they can only be locked by TXT, VT-d, CMD.LOCK.MEMCONFIG, ME_SM_LOCK or D_LCK. Finally, the addresses and sizes of these registers were partially wrong. Tested on Lenovo X201i with a Core i3 330M (no AES-NI, no VT-d and no TXT support compared to the Core i5 and Core i7 processors of a X201). Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b Signed-off-by: Matthias Gazzari <mail@qtux.eu> Reviewed-on: https://review.coreboot.org/25914 Reviewed-by: Nicola Corna <nicola@corna.info> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-30nb/intel/fsp_rangeley: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: I0b969a5109276d108e6140bad338c74786b967f3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-30nb/intel/i440: Get rid of device_tElyes HAOUAS
Use of `device_t` has been abandoned in ramstage. Change-Id: Ibd01659f518b7a2b1aaf334fe5b16cfb936b68b7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/23672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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