| Age | Commit message (Collapse) | Author |
|---|
|
All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
The newline lint check just went in, and immediately broke the build
due to a commit that went in earlier today.
This fixes the build.
Change-Id: Ic4ba8ce0c8085861bc6c654afdee3fea9f4621fc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
There are 4 routines used in RAM init that most if not all
i440bx mainboards call in the same order. Implements a single
RAM init routine for them to allow for future consolidation.
Boards to be changed to use this one routine in a future change.
Change-Id: Ib553b07b117de12b7982586bce0f9355f55013a0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This move makes the NB macro more widely available,
in preparation for implementing get_top_of_ram().
Change-Id: Icd8e82cfdfdccb662b2139d0e5d1d5af72cbae7f
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This does the following:
* Clarify that settings are set to the same value for each rank;
* Allows to program coarse
* Fix some style issues like white spaces between arithmetic
operators.
Change-Id: I3a9e28cfec915a0bb15789c23bea259f621b5096
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This does not use loops to compute timings but uses DIV_ROUND_UP.
Another thing affected by this patch are minimum timings. Presumably
those only need to be guarded against on DDR3. With this change
timings are set up like vendor (with tWTR below previous minimum)
TESTED on Intel D510MO
Change-Id: Ia374f26e5bbb8b90d90c24ae6c20412ba53bd7b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: Ic7132cd1848a75043d10f32ac5d0e6b45d2e0fe4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: I1944fcca91ee1a0ad8df5c8b6f402e907de5e78f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: I772d680774890c32ca6dc9b1e2143b3ab3bf6513
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: Ifc921d7aa2d5b771fc4eaf3ec776c3a13f5496eb
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add and use new interface to set and get GNVS' ASLB register.
To be used by Intel's gma driver to set ASLB at ACPI table
creation and to get ASLB on S3 resume.
Change-Id: If30c6b2270069783b0892774802f47406404da5f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use new GMA driver method to set ASLS.
Change-Id: I872ff86a778497df76ad7f9b1b6910c4e7c5941f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: Id1ed2252ce3ed052730dd10b24c453c34c2ab4ff
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
DIMMB's DDR width is in bit 20, not bit 19.
Change-Id: I48866d9243c2a576a02519724429801ae47c5644
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.
Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
DISPPLANE_BGRX888 defined in drivers/intel/gma/i915_reg.h
included in i915.h file
Change-Id: I4e9414f39a29e4eac7e325672ce6520a5654d3bc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: Ic01bbae9acaabaade777db52825aa80d25fc5961
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
The ALSB gnvs variable is used to load the OpRegion memory
address into the ASLS register on the S3 resume path, and must
therefore first be set on the normal boot path.
This patch brings Haswell in line with SNB/IVB/Nehalem, which
already save the OpRegion address in ASLB.
Change-Id: Ie062cbfe7e7f60c2a4e2b9111f6b6da87ced7a39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Needed to generate cpu entries.
Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Code checked manually
Change-Id: Idf86546ddda4fa2b4b96f0b703c03af9931c757d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Fill in acpi_name to return proper ACPI names. To be used with
SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
GFX0 is used in drivers/intel/gma/acpi/pch.asl.
MCHC is used in nb/intel/sandybridge/acpi/hostbridge.asl.
Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
On boards that are able to take two DIMMs per channel the
command rate should be 2T. It is possible to use 1T with
load reduced "1T" DIMMs, but it's not clear how to detect
those DIMMs. Raminit might fail for those who do not have
such DIMMS installed.
Hardcode command rate of 2T to make sure raminit works on
dual DIMM per channel boards (currently only desktop boards).
The command rate of 1T is still tested if only 1 DIMM per
channel is present.
Will decrease performance on quad slot mainboards, if two DIMMs
are installed in one channel and previously 1T have been selected.
Tested on ASRock B75 Pro3-M.
Change-Id: I029d01092fd0e11390cebcd94ca6f23bf0ee2cab
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Maybe we could go on, but cbmem_add() failing is a very bad sign.
Should fix coverity CID 1376384 (Null pointer dereferences
(NULL_RETURNS)).
Change-Id: I330cee6db3540c6a9c408d56da43105de5d075f7
Found-by: Coverity Scan #1376384
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20280
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
These delays, adding up to 600 ms, don’t seem to be needed, so remove
them.
TESTED on d510mo, boots fine without.
Change-Id: If089d6677fe95b086eeb00540acfbb66fa2e1c47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
|
|
Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older
Haswell MRC binary doesn't populate the pei_data struct with
all the info needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Use common init_igd_opregion method and remove duplicated code in
acpi.c.
Change-Id: I811e8bd2be68813321dc4581af02e1c21b0da076
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add method gma_write_acpi_tables.
No need to update GNVS as it doesn't have ASLB.
Change-Id: Ia138cfde2271a298c36b85e999ff69f0f211ba11
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Use common init_igd_opregion method.
Change-Id: Ia10a28d05b611a59f787b53f9736b3b76a19ea4a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Use common init_igd_opregion method.
Change-Id: Ic8a85d1373f04814b4460cce377d6e096bcdc349
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Too low gfx_uma_size can result in problems if the framebuffer
does not fit.
This partially reverts: 7afcfe0 "gm45: enable setting all vram sizes
from cmos"
Change-Id: I485d24198cb784db5d2cfce0a8646e861a4a1695
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Also changes the arguments of some functions to const.
This reduces romstage size by a whopping 1009 bytes.
Change-Id: I054504412524b7be19d98081097843b61bc0c459
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
The previous code seemed weird and tried to check if its selected
value is supported three times.
This also lower the clock if a selected frequency does not result in a
supported CAS number.
Change-Id: I1df20a0a723dc515686a766ad1b0567d815f6e89
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
The previous code seemed weird and tried to check if its selected
value is supported three times.
This also lower the clock if a selected frequency does not result in a
supported CAS number.
Change-Id: I97244bc3940813c5a5fcbd770d71cca76d21fcae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Use common init_igd_opregion method.
Change-Id: Ie70a49fd532b7ad7679dc558cc4a019a273a0602
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Copy Haswell's init_igd_opregion to common folder.
Remove platform specific code.
Will replace all Intel NB implementations.
Change-Id: I14dfb5986df264ffd71183a159f98b79e8e3230e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Switch from lapic to tsc.
Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.
Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.
Tested on Lenovo T430.
Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Provide all gfx init methods as a Kconfig `choice`. This elimates the
option to select native gfx init along with running a Video BIOS. It's
been only theoretically useful in one corner case: Hybrid graphics
where only one controller is supported by native gfx init. Though I
suppose in that case it's fair to assume that one would use SeaBIOS to
run the VBIOS.
For the case that we want the payload to initialize graphics or no
pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the
choice. If multiple options are available, the default is chosen as
follows:
* NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS,
* VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS,
* NATIVE_VGA_INIT, if we don't add a Video BIOS.
As a side effect, libgfxinit is now an independent choice.
Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the
reference clock can be 100Mhz.
Decode the register and use the reference clock to calculate
the selected DDR frequency.
Tested on Lenovo T430.
Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put
it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are
two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt
and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for
`HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model
that with additional symbols.
Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers
that support a linear framebuffer. Some related settings moved to the
drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are
hardcoded.
Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.
Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The deprecated LATE_CBMEM_INIT function is renamed:
set_top_of_ram -> set_late_cbmem_top
Obscure term top_of_ram is replaced:
backup_top_of_ram -> backup_top_of_low_cacheable
get_top_of_ram -> restore_top_of_low_cacheable
New function that always resolves to CBMEM top boundary, with
or without SMM, is named restore_cbmem_top().
Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
It could end up not initialized which causes it not to build with
clang.
Change-Id: I3be9477d836123aaa87c9bebb41c1ec34689a771
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I3cd5e99b9954a68837de85b49b4389b668e00cf4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
This makes the code more readable since it avoids messing with two
dimensional arrays and needing remember what the indices mean.
Also introduces an unused coarse element which is 0 for all default
DLL settings on DDR2.
Change-Id: I28377d2d15d0e6a0d12545b837d6369e0dc26b92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Hides JEDEC steps using the RAM_SPEW macro.
Also hides a hexdump of SPDs.
Change-Id: Ie2b484cf1f1d296823df0473e852d9d07ca20246
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This improves readability.
Change-Id: Ib4387a4f4092053dab273191a73edb0ef31a79f6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
It is not really known why there is such a long delay, but it works
fine without it.
TESTED on ga-g41m-es2l.
Change-Id: Idff5b978bbf161f8520d8000848e7b11c98c3945
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19514
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Hide device 4 and device 7 if disabled.
Allows devicetree settings to take effect.
Tested on Lenovo T430.
Change-Id: I64a19e2bbdb1640e1d732f6e4486f73cbb0bda81
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
A left-over from 5e3cb72a71 (nb/x4x: Do not enable IGD when not
supported). Should fix coverity issue 1375009. Remove a redundant
line that uses the variable `gfxsize` out of its scope and move the
variable declaration. Make sure the variable is always initialized,
drop unneeded error-handling for `get_option()` and sanitize the
read value instead.
Change-Id: Iee2beda30d8c74df0f412622c3ff3357819e386b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19680
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
`cardF[n]` should indicate whether the DIMM in channel n is of
raw card type F. However, `cardF[1]` was initialised with the
value meant for `cardF[0]`. This patch results in the correct
initialisation of `cardF`.
Tested on a Lenovo T400 containing two DIMMs: one of raw card
type F and the other of raw card type B. Before the patch, the
system would not boot. After the patch, the system boots with all
of the memory functional.
Change-Id: I7409df0b8c67d7efbdadae39dc718c8df7a92552
Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Reviewed-on: https://review.coreboot.org/19652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This results in raminit_receive_enable_calibration.c producing
no errors or warnings with checkpatch.
The issues fixed are:
ERROR: that open brace { should be on the previous line
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
Tested by compiling after making the changes.
Change-Id: I8d2f4f1fe2f17aa44c0a7090c178eee418defe78
Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Reviewed-on: https://review.coreboot.org/19651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Currently only one board uses this northbridge in coreboot but some
patches are pending to add more.
Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I2308b069b8f2c601254169bcb6a34442c537a311
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I15550b1cc1a7ccfecba68a46ab2acaee820575b9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Is only present on the P45 subtype of chipset.
Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
According to "Intel ® 4 Series Chipset Family datasheet" in the
description about GGC and DEVEN, CAPID0 bit46 is said to reflect the
presence of an internal graphic device. This would allow the P43 and
P45 chipset variants to work.
Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18515
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The NGI writes to legacy VGA registers which should not happen when
VGA cycles are assigned to a different device.
TESTED on ga-g41m-es2l
Change-Id: I0a03e35c0d7f2532edd6cc5e62d1cf07dab57f60
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This disables VGA cycles on IGD when an external VGA device is
found. This allows PCI or PCIe devices to be the 'main' VGA device if
found, while the IGD is still available.
TESTED on ga-g41m-es2l: SeaBIOS shows payload on external GPU while
linux (4.10) can use both as a framebuffer simultaneously without any
extra configuration.
Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Computes TSEG size dynamically.
Changes the size of legacy hole to match other Intel northbirdges.
Refactor this a little by needing one less variable.
Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This code ought not to run if ME is disabled. It also prohibits
writing to some GMCH regs like GGC bit1.
Intel ® 4 Series Chipset Family datasheet refers to this as
"ME stolen Memory lock" without actually describing this
functionality.
Change-Id: Iaa8646e535e13c44c010ccd434a5af954cf7dfbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Use names instead of magic values.
No functional change.
Change-Id: I3774595ff0fd21e42dc407ca8a0cf3fd7788a66f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Use register name instead of hex value.
No functional change.
Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
The checkreset() function checks if raminit previously
succeeded (pmcon2 bit7 == 0). If this is not the case it will issue a
hot reset (writing 0x6 to 0xcf9). On the next attempt to boot the
system BOOT_PATH_RESET path will be taken. This boot path can only
successfully initialize memory if the system was reset from a state
where raminit succeeded, which is not the case here.
This can be fixed by issuing a cold reset instead of a hot reset.
Change-Id: Idbcf034c3777a64cc3fb92dc603d10470a6c8cb6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add some known good values for some thinkpads displays.
Known good means that at this pwm frequency the display is evenly lit
on all duty cycles, the display makes minimal to no noise at lower
duty cycles and the display does not flicker. This values differs from
vendor (which uses an obviously wrong display clock (190MHz instead
of 320MHz) resulting in frequency more than 60% off the intended
value.
TESTED on Thinkpad X200 with edid ascii string in list and removed
from list to see if notice message is shown.
Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This allows to use EDID data outside of NGI path without needing to
fetch it twice.
Change-Id: I6a540b1d036a9f38b44fd004309601630861f6e7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: I97c3402ac055991350732e55b0dda042b426c080
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: I76b31fe5fd19b50b82f57748558fb04408e0fd23
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19309
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Set up IGD OpRegion in northbridge and fill in GNVS' aslb.
At this point GNVS already has been set up by SSDT injection.
Required for future VBT patches that will:
* Use ACPI memory instead of CBMEM
* Use common implementation to locate VBT
* Fill in platform specific values
Change-Id: Ie5d93117ee8bd8d15085aedbfa7358dfcf5f0045
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19307
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This is not needed.
Change-Id: Id19a00c1546b7a71d90aa8c7e43e6efde1e9fbbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19425
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19333
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: Id1b7b98b4fba745ac0d55638b6a5cceba3c329ef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19415
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
TESTED on D510MO.
Change-Id: I05aa40df0d2a090fcf734416669e9e1bbff094e4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19414
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
For raminit to succeed on a hot reset the following things are
prevented from running:
* Clearing self refresh
* Setting memory frequency
* programming sdram dll timings
* programming rcomp
TESTED on Intel d510mo.
Change-Id: I8f7e5c2958df29a96cdf856ade2f4f33707ad362
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19337
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Clean up NGI code now that libgfxinit has replaced old C code:
- replace #if preprocessor guards with if (IS_ENABLED(...))
- don't guard variable declarations
- remove code that would only be executed for old NGI / isn't
used by libgfxinit
Test: boot google/wolf with VBIOS, NGI, and UEFI/GOP video init,
observe payload and pre-OS graphics display functional.
Change-Id: I96e74f49ea70e09cbac6f8af561de3e18fa7d260
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19327
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
The function decode_spd uses undeclared variables and an incorrectly
initialized array.
Change-Id: Ib45a8b2946c04c270e29524675b1f09d491d282b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19336
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ib92550fe755293ce8c65edf59242a2b04327128e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19332
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Hide some (partial) lines behind DEBUG_RAM_SETUP and shorten
some messages. This saves some KiB to make CBMEM console more
usable in romstage.
Change-Id: I62a84ca662ee778b7c1deb71247f3b01a37858fa
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
The x4x northbridge can be paired with either an ICH7 (in the case of
g41) or an ICH10 (all other cases: g45, q45, p45, ...). Only ICH10
sometimes occurs with a descriptor, gbe and an ME region.
ICH7 is always descriptorless so it makes no sense to fix CBFS to
accommodate for those other objects.
Change-Id: I4a01dfdbce1807e44932a3ac812110382332abd8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19181
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203).
Not running PCIEx16 init which is valid for 945gm seems to fix all
issues and instabilities related to the PEG port.
According to lspci the link width is at the desired x16.
It is unknown if devices requesting a lower width work automatically
or need more configuration.
What happens is that IGD gets disabled by the disable function in
gma.c when an external GPU is found unless
CONFIG_ONBOARD_VGA_IS_PRIMARY is set.
Setting IGD as secondary makes Linux (4.10) hang, so this behavior is
a requirement for now.
TESTED on P5GC-MX with a discrete GPU and both
CONFIG_ONBOARD_VGA_IS_PRIMARY set and unset.
Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18549
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
All boards select INTEL_EDID, move it to nb folder.
Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19086
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Move odt stretch into own function.
Apply workaround on SandyBridge C-stepping CPU only.
Apply odt stretch on all other CPU types.
Don't depend on empty DIMM detection, as in case one slot
is empty ref_card_offset is zero.
Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17616
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
quick_ram_check doesn't change contents of memory.
Run it in S3 resume, too.
Change-Id: Icaf3650fadbb3bb87d8c780a9e79737c3cf7eb06
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17615
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
Silency noisy raminit logging by:
* Removing verbose logging from loops.
* Printing detailed summary at end of loop instead.
* Using the same scheme already present in some functions.
Change-Id: I412d81592436ac0d2422caf396c64e0c34acc2d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17611
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Remove cross rank/cross channel dependency.
I guess this is a mistake that could lead to instabilities.
Tested on Lenovo T430 (Intel IvyBridge).
Change-Id: I899db907cd2d2197fd81eda4c4656fb1e570c18f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17610
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
|
|
Add 100 Mhz reflock default values for Ivybridge.
Some values are extracted from MRC, those marked as
guessed needs to be verified.
Tested on Lenovo T430 (Intel IvyBridge) and DDR3-1800.
Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17609
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Add debugging output to normalize_training.
Tested on Lenovo T420.
Change-Id: I1d787f7ead6cf35ee142a8848837840c91cb6967
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17608
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
|
|
Add support for 100MHz reference clock on ivybridge.
Allows to use more frequencies than sandybridge.
Tested on Lenovo T430 (Intel IvyBridge) on DDR3-1800.
Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17607
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Use Ivy Bridge specific magic values on Ivy Bridge instead
of Sandy Bridge values.
The values are extracted from MRC.bin.
Should increase raminit stability.
Tested on Lenovo T430 (Intel IvyBridge).
Change-Id: I49fdfe5ae3e65704d22e083e8446e3f1069869bc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17606
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Move header and delete duplicates.
Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18903
Tested-by: build bot (Jenkins)
Tested-by: coreboot org <coreboot.org@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Some Chrome OS boards previously didn't have a hardcoded vboot
configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE,
etc.) selected from their SoC and mainboard Kconfig files, and instead
relied on the Chrome OS build system to pass in those options
separately. Since there is usually only one "best" vboot configuration
for a certain board and there is often board or SoC code specifically
written with that configuration in mind (e.g. memlayout), these options
should not be adjustable in menuconfig and instead always get selected
by board and SoC Makefiles (as opposed to some external build system).
(Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for
Pistachio/MIPS was never finished. Trying to enable even post-romstage
vboot leads to weird compiler errors that I don't want to track down
now. Let's stop pretending this board has working Chrome OS support
because it never did.)
Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19022
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This is a cosmetic change.
Change-Id: Iea4dd97e9d83594447427abd9f844e507b805192
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18960
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Currently the `break` further down is called unconditionally as the
brackets for the body of the if statement are missing. Add those.
Change-Id: I34917a9877dcc882d880dedea689e1d72fe52888
Found-by: Coverity (CID 1372941: Control flow issues (UNREACHABLE))
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18971
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18704
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
