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2022-09-14nb/intel: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6d0d945011fa046b974c6f4554cb9fb15e523afb Reviewed-on: https://review.coreboot.org/c/coreboot/+/67578 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26nb/intel/sandybridge: Align TOUUD down to 1 MiB granularityArthur Heymans
This register has a 1MiB granularity. The lowest bit is a lock bit. Change-Id: I688cb7818fc849784026ca0bc6acb7ef1ae92133 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66256 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-17commonlib/clamp.h: Relicense file to be BSD-compatibleAngel Pons
I added this header in commit a6c8b4becbd12fe6043557ca1e398c1a7c691007 (nb/intel/sandybridge: Rewrite get_FRQ). Relicense it as "BSD-3-Clause OR GPL-2.0-or-later" and move it into the BSD-licensed commonlib part. Change-Id: I89ebdcdf8d06e78e624e37a443696981b3b17b7d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66711 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-17nb/intel/sandybridge/raminit_mrc.c: Use semicolon instead of commaElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I15d7e2f30b054d14009761006a2f89f45e001118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-07-14northbridge/intel/i945: Fix GCC optimizing out cache preload jumpPetr Cvek
Clock config setup must be run from cache. Original code used "goto" to prefetch the code required to update the VCO (by jumping after the code and back before). The GCC since at least 12.1.0 and clang since at least 13.0.1 will elimitate these jumps. Use inline assembler to force the original code flow. TEST=Verified assembly code is the same as generated by GCC 12.1.0 and boot tested on Kontron 986LCD-M. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: I67c2072b5983a5bd845631af136ae5a003c7ea3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-05nb,soc/intel: Handle upper RAM boundaryKyösti Mälkki
Change-Id: I2d99523647dfb43265db8f2701b525afd1870fc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-30nb/intel: Drop local legacy_hole definitionsKyösti Mälkki
These are architectural and followup works will address the VGA MMIO and/or ASEG better. Change-Id: I88e1dca8058661e31ba934b9860751e13a107108 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55928 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-24device/resource: Modify some resource allocation instancesKyösti Mälkki
These changes made my crude pattern matching work with coccinelle simpler. Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-24nb/intel/gm45/acpi: Fix max PCI bus numberNico Huber
Commit 0cc56a2848 (nb/intel/gm45/dsdt: Fix number of PCI busses) derives the maximum PCI bus number at runtime. However, IASL complains about the initial 0 in the resource template, which rendered the PB00 definition self-contradictory at build time (maximum was lower than minimum + length - 1). Let's return to the old default values (min: 0, max: 255, length: 256) and adapt max and length at runtime. Also fix some surrounding whites- pace. NB. The issue wasn't detected before merging commit 0cc56a2848 because of broken IASL versions that can't count errors. Change-Id: I359d357f276feda8fe04383080d51dc492c3f2e8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64347 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Stefan Ott <coreboot@desire.ch> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-22device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki
There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-20intel/gma: Use bitwise or instead addition for valid bitPetr Cvek
Page table entries bit 0 is used as "valid". Its value should be set by a bitwise OR and not by an addition. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: I14467081c8279af4611007a25aefab606c61a058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-06-02nb/intel/i440bx: Use PARALLEL_MPArthur Heymans
The ramstage size is decreased by roughly 5K, but the compressed size increased by ~1K. Change-Id: Ic8d2582b353069eecea8561cfe01b2dd8221779b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59693 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-24nb/intel/i945,gm45: Use incrementing index with fixed resourceKyösti Mälkki
Do this for consistency, while followup will remove the index completely. Change-Id: I7b4822c3909801e91627ed2ffe776d65dfab08d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16northbridge/intel/i945: Convert to ASL 2.0Elyes HAOUAS
Change-Id: Iea9630ce7e5bfcc9d1c8699a81bd1c61a0705de8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16src: Remove unused <cf9_reset.h>Elyes Haouas
Found using: diff <(git grep -l '#include <cf9_reset.h>' -- src/) <(git grep -l 'RST_CNT\|FULL_RST\|RST_CPU\|SYS_RST\|do_system_reset\|do_full_reset\|cf9_reset_prepare\|system_reset\|full_reset' -- src/) |grep "<" Change-Id: I093d8412e14ce81b462fb9a7ccb3a2a93ae760a6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-13nb/intel/snb/raminit_mrc.c: Remove set but unused variableArthur Heymans
Change-Id: I1cf656b404b0e880c061b273ef259ca40a6d499a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-13nb/intel/gm45: Enable 64bit supportArthur Heymans
This patch does the following: - Allow selecting 64bit from Kconfig - Fix up integer to pointer conversion that gcc complains about - Add a buildtest target in configs Tested on Thinkpad X200: boots fine to the payload Change-Id: Icb9c31a28ee231b87109b19c00ce2f8b48b5aefe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-13nb/intel/gm45/iommu.c: Fix clearing GTTArthur Heymans
This was dead code as it was checking for the wrong bit (bit 11 indicates the use of shadow GTT). It was doing it at the wrong place regardless as no BARs are set up. Move the code clearing GTT into the GMA .init code and do it unconditionally: if the GTT does not match 2M then the cycles are simply not decoded. Tested on thinkpad X200. Change-Id: Iac3264d484e66e9ca4b3cd3df90ad87a476e31ce Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-13nb/intel/gm45/dsdt: Fix number of PCI bussesArthur Heymans
Linux complained that the numbers in DSDT (256) don't match with the values in MMCONF (64). Change-Id: I2ccac64934e8d284e68945f86ec46cb2bf896277 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-05-13nb/intel/gm45: Allow for PCI BARs above 4GArthur Heymans
Linux needs to know that allocating BARs above 4G is fine so reserve a region in ACPI for that. Tested on thinkpad X200: a PCIe window gets allocated above 4G and Linux does not relocate it. Change-Id: I62a8a656481eba01add3d7d06b42e3352206df1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-04-27nb/intel/pineview: Use cbfs mcacheArthur Heymans
There is plenty of cache available to increase DCACHE_RAM_SIZE to allow the use of cbfs mcache. Tested on Gigabyte GA-D510UD, still boots and resumes. Change-Id: I1487ba9decd3aa22424a3ac111de7fbdb867d38d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-24northbridge/intel: Remove unused <acpi/acpi.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: I72a0f26b79cf0f61338876cf58d143f7ef3cad3b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-22nb/intel/i945/memmap.c: Fix TOLUD bit field maskPetr Cvek
Register TOLUD is defined as bit field 7:3 (section 5.1.26, page 103, i945GM datasheet), fix the mask accordingly. Change-Id: Ia27661084e11ea93d5f0dc20bafb488ae2995b49 Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-04-20nb/intel/snb: Reduce scope of functionsArthur Heymans
Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-10nb/intel/sandybridge: Restore `mainboard_early_init()` callAngel Pons
Commit 7a874330919a4df9cc5b66058b4340465b7ea041 (mb/google,samsung: Drop init_bootmode_straps()) got rid of the `mainboard_early_init()` function call and weak definition in Sandy Bridge code. However, this function is still used by several Sandy Bridge mainboards, so bring back the dropped call and weak definition. The aforementioned commit did not cause any build-time errors because it did not remove the `mainboard_early_init()` function declaration. Change-Id: I82768e9a187696d42b61be44d4aa048acc19d551 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-04-09mb/google,samsung: Drop init_bootmode_straps()Kyösti Mälkki
Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-28nb/intel/sandybridge/acpi: Support setting PCI bars above 4GArthur Heymans
Although coreboot can allocate resources above 4G, Linux does not consider those allocation valid when there is no region above 4G in _CRS and disables the device. TESTED: x220 with and external GPU via the expresscard slot. Linux does not touch the BARs allocated above 4G. Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2022-03-25nb/intel/gm45/pm.c: Make clang happyArthur Heymans
Clang complains that the terniary '?' operator is executed before the bitwise '|'. This is true and desired in this case. Being explicit about won't hurt however. Change-Id: I27d1fc1c19e1dab3d1c82e407151eaa46f8c7b03 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-25cpu,mb,nb,soc: use HPET_BASE_ADDRESS instead of magic numberFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I570f7de90007b67d811d158ca33e099d5cc2d5d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62308 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25arch/x86: consolidate HPET base address definitionsFelix Held
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO region which is 0xfed00000 on all chipsets and SoCs in the coreboot tree. Since these two different constants are used in different places that however might end up used in the same coreboot build, drop the Kconfig option and use the definition from arch/x86 instead. Since it's no longer needed to check for a mismatch of those two constants, the corresponding checks are dropped too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-24nb/intel/ironlake: Clean up `jedec_read()` functionAngel Pons
Deduplicate a condition and reflow some lines. Tested on HP ProBook 6550b, still reaches TianoCore payload. Change-Id: If5786f34585e15100385d452b5b03a36da4c7c87 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-24nb/intel/ironlake: Fix some quickpath init magicAngel Pons
Correct some Quickpath initialisation steps according to findings from two different Intel reference code binaries as well as MCHBAR register dump comparisons between vendor firmware and coreboot. The MSR_TURBO_POWER_CURRENT_LIMIT information comes from EDK2 sources. Tested on Apple iMac 10,1 (Clarkdale, aka desktop Ironlake), QPI init now completes successfully instead of causing hangs before raminit. Also tested on HP ProBook 6550b (Arrandale, aka mobile Ironlake), still reaches payload (e.g. TianoCore). Change-Id: Icd0139aa588dc8d948c03132b5c86866d90f3231 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-24nb/intel/ironlake: Move out HECI remainders into southbridgeAngel Pons
Move the remaining HECI-related stuff to southbridge scope, as the HECI hardware is in the southbridge. Note that HECI BAR is now enabled a bit earlier than before, but this shouldn't matter. Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-16Use the fallthrough statement in switch loopsArthur Heymans
Clang does not seem to work with 'fall through' in comments. Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-15nb/intel/ironlake/raminit_heci.c: Move to southbridge scopeAngel Pons
HECI stuff is in the southbridge, so put the code in there. Rename the file to match the name of the function it provides. Change-Id: I71de1234547dbd46a9b4959c619d2ae194da620a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake: Decouple `setup_heci_uma()` from northbridgeAngel Pons
Remove all northbridge dependencies in the `setup_heci_uma()` function. Update its signature to not pull in raminit internals and drop a dummy read that doesn't have any side-effects (it's probably a leftover from a replay of vendor firmware). This code will be moved into southbridge scope in a follow-up. Change-Id: Ie5b5c5f374e19512c5568ee8a292a82e146e67ad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake/raminit_heci.c: Turn into compilation unitAngel Pons
Remove the temporary `raminit_heci.c` include and make it a proper compilation unit. Export the `setup_heci_uma()` function. Change-Id: Ia6782a0cb5e731d58764d0fa4ee256bfc8cef98a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-15nb/intel/ironlake: Split out HECI code out of raminitAngel Pons
Move HECI code out of raminit.c into a separate raminit_heci.c file. To preserve reproducibility, use a temporary .c include. This will be gone in a follow-up. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I240552c9628f613fcfa8d2dd09b8e59c87df6019 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-05cpu,nb/intel: Drop remains of LAPIC_MONOTONIC_TIMERKyösti Mälkki
Leftover from using UDELAY_LAPIC on these platforms. Change-Id: I718050925f3eb32448fd08e76d259f0fb082d2d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-04nb/intel/haswell: Report SMBIOS memory speed in MT/sAngel Pons
The memory speed values in SMBIOS tables are expressed in MT/s, not MHz. Adjust the reported frequency values accordingly. Change-Id: If34827fee582ef10057e7540b9d23d8c74bd2a32 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61504 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-31nb/intel/gm45/raminit.c: Fix indent for 'if' statementElyes HAOUAS
Change-Id: I316ae56321da1183caefeac3163b8909d1a554b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use <device/dram/ddr3.h> macrosElyes HAOUAS
Change-Id: Icca870d1c97a2737dec3f31b0f2e4c3222c711ae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use DDR3_SPD_SODIMM macroElyes HAOUAS
Change-Id: Ibbb6e6d44b1415b18aa59310f4d36d61b9a2a080 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-27nb/intel/sandybridge/raminit_mrc.c: Use <smbios.h> macrosElyes HAOUAS
Use macros defined in <smbios.h> for 'ddr_type' and 'bus_width' Change-Id: I0501147139387cd9b5c7ec6b7ba7f8a5c5bd18bb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-26src: Add missing 'void' in function definitionElyes HAOUAS
Change-Id: I7fa1f9402b177a036f08bf99c98a6191c35fa0b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-25northbridge/intel/i945: Change types to uintptr_t where appropriateElyes HAOUAS
Prepares compilation for x86_64 by avoiding casts to different sizes. Current patch fixes: 1. src/northbridge/intel/i945/raminit.c: In function 'ram_read32': src/northbridge/intel/i945/raminit.c:77:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 77 | read32((void *)offset); | ^ 2. src/northbridge/intel/i945/rcven.c: In function 'sample_strobes': src/northbridge/intel/i945/rcven.c:29:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 29 | read32((void *)addr); | ^ src/northbridge/intel/i945/rcven.c:30:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 30 | read32((void *)(addr + 0x80)); | ^ 3. src/northbridge/intel/i945/gma.c: In function 'intel_gma_init_lvds': src/northbridge/intel/i945/gma.c:98:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 98 | (void *)pgfx, mmiobase, piobase, pphysbase); | ^ src/northbridge/intel/i945/gma.c:359:25: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 359 | (void *)pgfx, hactive * vactive * 4); | ^ src/northbridge/intel/i945/gma.c:360:24: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 360 | memset((void *)pgfx, 0x00, hactive * vactive * 4); | ^ src/northbridge/intel/i945/gma.c: In function 'intel_gma_init_vga': src/northbridge/intel/i945/gma.c:384:17: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 384 | (u32)mmiobase, piobase, pphysbase); | 4. src/northbridge/intel/i945/northbridge.c: In function 'mch_domain_read_resources': src/northbridge/intel/i945/northbridge.c:64:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] 64 | cbmem_topk = ((uint32_t)cbmem_top() / KiB); | ^ Change-Id: I5ac7a1cb5d85a346114f909047d5a7c21ddb43e9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-01-10src/{northbridge,southbridge}: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: I1205b1a27436853f2187d8ddd95f0bf9a853f986 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-05src/northbridge: Remove unused <delay.h>Elyes HAOUAS
Change-Id: I5449feeb65c49c79bc7657a1c3777a0f128a13b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-04nb/intel/i945/raminit.c: Set "integrated_graphics" as boolElyes HAOUAS
"integrated_graphics" is already used as a "bool" at line #2128. So set it as "bool". Change-Id: Ic5286e691c312e8e44bbbd8e782fdfd4a13cb60f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-01-01src: Use 'stdint.h' when appropriateElyes HAOUAS
Change-Id: I1df255d55b8f43a711d836c2565c367bd988098a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-01-01src: Drop duplicated includesElyes HAOUAS
<types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-30northbridge/intel/ironlake/acpi: Use Printf() for debug printsFelix Singer
Change-Id: I5d3af659255548e84ef676387ca994588c69438c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30northbridge/intel/sandybridge/acpi: Use Printf() for debug printsFelix Singer
Change-Id: I58c2545c881572127b6d34b5527c5d4bd7d97dfb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-30northbridge/intel/haswell/acpi: Use Printf() for debug printsFelix Singer
Change-Id: I3f500ec46a9046a4e8ca50a85965b8e1225f8a33 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-12-23nb/intel/ironlake: Use `NUM_CHANNELS` macroAngel Pons
Change-Id: I3f4dc26699e3618740af5a0ade1a19599d5a2cc7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-16Spell *Boot Guard* with a space for official spellingPaul Menzel
See for example Intel document *Secure the Network Infrastructure – Secure Boot Methodologies* [1]. Change all occurrences with the command below: $ git grep -l BootGuard | xargs sed -i 's/BootGuard/Boot Guard/g' [1]: https://builders.intel.com/docs/networkbuilders/secure-the-network-infrastructure-secure-boot-methodologies.pdf Change-Id: I69fb64b525fb4799bcb9d75624003c0d59b885b5 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-02nb/intel/sandybridge/romstage.c: Configure DPR and initialize TXTMichał Żygowski
Initialize the DPR register and check if SCLEAN needs to be run. Allows to reliably boot the platform if ungraceful shutdown occured or the memory controller has been locked by TXT. TEST=Dell OptiPlex 9010 with Intel TXT enabled boots successfully after 4s power button override or power cable unplug when SENTER was executed. Successfully boot QubesOS 4.0 with TBoot v1.8.2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I4b912f121593fa55c11813262f09be1a1055e950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-26nb/intel/sandybridge: Add support for DPRMichał Żygowski
Include DPR in the memory map calculations if enabled. DPR is required for Intel TXT support. TEST=Boot Debian 10 and see the DPR memory being reserved in E820 and cbmem logs: "BIOS-e820: [mem 0x000000007fc09000-0x00000000829fffff] reserved" "TSEG base 0x80000000 size 8M" "DPR base 0x7fd00000 size 3M" Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11haswell/lynxpoint/broadwell: Use `azalia_codec_init()`Angel Pons
Use the functionally-equivalent common Azalia code to get rid of redundant code. Change-Id: I83cf1a3a1a3854c9283ccac5e254357a32638dda Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59118 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik
List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05nb/intel/haswell/northbridge.c: Drop stale commentAngel Pons
This can now be controlled with the `MMCONF_BUS_NUMBER` Kconfig option. Change-Id: If0fdefc5b4339acc843443c551892b397ed39c2e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-04nb/intel: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I617fea8a09049e9a87130640835ea6c3e2faec60 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-10-18ACPI: Have common acpi_fill_mcfg()Kyösti Mälkki
As long as there is only one PCI segment we do not need more complicated MCFG generation. Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-13nb/intel/haswell: Add HDAU ACPI deviceMatt DeVillier
The HDAU stub device enables HDMI audio under MacOS. Change-Id: Ifa2155512dd909a4e4a753f6475541e9410dfe91 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-11nb/intel/sandybridge: Populate meminfo when using MRCMatt DeVillier
Populate a memory_info struct with PEI and SPD data, in order to inject the CBMEM_INFO table necessary to populate a type17 SMBIOS table. On Broadwell, this is done by the MRC binary, but the older Sandy Bridge MRC binary doesn't populate the pei_data struct with all the info needed, so we have to pull it from the SPD. Some values are hardcoded based on platform specifications. Change-Id: I15e00a01121150b778cfa684b9147d0cac97beb8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-02nb/intel/haswell: Move MRC glue code into a subfolderAngel Pons
Put the Haswell MRC glue code inside a `haswell_mrc` subfolder. Future commits will move the Broadwell MRC/refcode glue code to be in Haswell northbridge scope, so plan in advance. Tested on Asrock B85M Pro4, still boots. Change-Id: Id3e26ec1c2d5ccce928083d7ce41445908df8cf3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55523 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-02nb/intel/haswell/gma.c: Add ULX PCI device IDsAngel Pons
Change-Id: Ida3d2dcdf89342b084c8e1fbf3fae7e47a7238d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50137 Reviewed-by: Jamal Wright <Crabstorage@getbackinthe.kitchen> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06nb/intel/x4x: Expose x86_64 supportArthur Heymans
TESTED on foxconn g41m. Change-Id: I2d5d5dfbd76a84aa400e44b4bc2ac4f3b5b6f739 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56022 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05nb/intel/x4x: Use write32p and read32pArthur Heymans
This removes the need for type conversions all over the place. Change-Id: I633a453aff17f1cbbe06b60e3efb67661733d06c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56029 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05nb/intel/x4x: Prepare for x86_64 supportArthur Heymans
Do the usual type conversions TESTED: Same image with BUILD_TIMELESS=1 Change-Id: Id44eeb7660d0b521a326a5b981c04c16cf0a6f84 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56019 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-22nb/intel/haswell/pcie.c: Avoid needless deathAngel Pons
Using `config_of(dev)` to access `dev->chip_info` will make coreboot die if the latter is NULL, which is the case for devices detected at runtime (i.e. not statically declared in the devicetree). Given that the code is designed to work when the PEG config is all-zeroes (devicetree default), dying because `dev->chip_info` is NULL is foolish and unwarranted. Introduce a helper function that returns a pointer to devicetree config when available, and otherwise returns a pointer to a zero-filled static struct. In addition, avoid an out-of-bounds access in the very unlikely case where the device's function is too large. Tested on Asrock B85M Pro4, can now boot when `device pci 01.0 on end` is commented out in its devicetree. Without this commit, it could not. Change-Id: Ia2d3a03da9eab601fb834b0c51a8a51c9ae14c33 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-22nb/intel/haswell/pcie.c: Introduce helper variableAngel Pons
Introduce a helper variable to avoid some redundancy and to reduce the diffstat noise in follow-up changes. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I490675aaddd2b5a13d990664431f79a605999254 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-22nb/intel/haswell/pcie.c: Fix getting PCI functionAngel Pons
Use `dev->path.pci.devfn` to obtain the `devfn` that `PCI_FUNC` needs. Tested on Asrock B85M Pro4, `PCI_FUNC` now obtains the correct value. Change-Id: Ia3bbd56ce0adba9d24f62ffc016cd825bcf3cc6a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-06-17nb/intel/ironlake: Factor out common uncore ASLAngel Pons
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I7e37d32251fa3dcc64aec62dd2d814463c4a9999 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55580 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16MRC platforms: Fix MRC version printk format specifiersAngel Pons
The printed values are unsigned, and should be printed accordingly. Change-Id: Ie5edce914c389c70460b1ed3390731e3568340dd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16nb/intel/haswell: Fully handle GDXCBAR and EDRAMBARAngel Pons
GDXCBAR and EDRAMBAR are accounted for when reporting resources to the allocator, but they are not present in the DSDT. In addition, coreboot does not enable either range, but MRC.bin sets up GDXCBAR and does not disable it afterwards. Not reporting GDXCBAR in the DSDT can result in resource conflicts, and not enabling EDRAMBAR can cause issues on CPUs with eDRAM. Enable both GDXCBAR and EDRAMBAR in coreboot code, and report these ranges in the DSDT. This matches what Broadwell does. The value for the `GDXC_BASE_ADDRESS` macro matches what MRC.bin programs as well. Tested on Asrock B85M Pro4 with an i7-4770S (no eDRAM): - Still boots - EDRAMBAR is now enabled with base address of 0xfed80000 - GDXCBAR is still mapped with base address of 0xfed84000 Change-Id: I5538873b30e3d02053e4ba125528d32453ef6572 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16nb/intel/haswell/memmap.h: Define MMIO window sizesAngel Pons
Add defines for the sizes of northbridge MMIO windows and use them where applicable. The macro names have been taken from Broadwell. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I845cba8acbd478cd325d2e364138336d985f9c34 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-16nb/intel/haswell: Update some "Misc ICH" commentsAngel Pons
One of the Memory32Fixed entries covers the TXT private and public spaces, and another covers the TPM registers. Update the comments. Change-Id: I261d74c113fabf1d152964efd8c91de85eba4179 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-15nb/intel/sandybridge: Add x86_64 supportPatrick Rudolph
Fix compilation on x86_64 by using compatible types. The MRC blob isn't supported yet as there's no x86_32 wrapper. Tested on HP8200: * Still boots on x86_32. * Boots to payload in x86_64 Change-Id: Iab29a87d52ad3f6c480f21a3b8389a7f49cb5dd8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-10nb/haswell/gma: Add Desktop GT1.5 (HD 4400) Device IDMate Kukri
Change-Id: Idc7c38206b1ddfe486298cd3921fcb762a89ec51 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55243 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-07cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28nb/intel/x4x/rcven.c: Guard macro parametersAngel Pons
Add parentheses around macro parameters to avoid operation order issues. Change-Id: I9528f3d6b221854fddd2db6d2b45c63bfdda0092 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54953 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-27lib/hexdump: remove hexdump32 and use hexdump insteadFelix Held
hexdump and hexdump32 do similar things, but hexdump32 is mostly a reimplementation that has additional support to configure the console log level, but has a very unexpected len parameter that isn't in bytes, but in DWORDs. With the move to hexdump() the console log level for the hexdump is changed to BIOS_DEBUG. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6138d17f0ce8e4a14f22d132bf5c64d0c343b80d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54925 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16nb/intel/gm45: Guard even more macro parametersAngel Pons
Add brackets around the parameters to avoid operation order problems. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: Icb9d6e8bdafdac7ad820b1629d04e7bdfbcd4b3f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-05-07nb/intel/e7505: Fix for RESOURCE_ALLOCATOR_V4Kyösti Mälkki
Memory region 0xa0000 to 0xc0000 was not reserved, the first PCI memory resources might get assigned in this space. FIXES: aopen/dxplplusu PCI EHCI 0:1d.7 memory resource. Change-Id: Ia17025bde83b91d71ad719de6348197cf92e267e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-05-06src: Retype option API to use unsigned integersAngel Pons
The CMOS option system does not support negative integers. Thus, retype and rename the option API functions to reflect this. Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-05-05nb/intel: Don't select VBOOT_SEPARATE_VERSTAGEArthur Heymans
Now the bootblock is not limited to 64K so integrating vboot into the bootblock reduces the binary size. Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03nb/intel/common: Replace `_bar_clrsetbits_impl` macroAngel Pons
This macro contains a cast on the and-mask, which can suppress actual type overflow issues. Replace it with wrapper functions around the existing macros in device/mmio.h which still contain a type cast, but it is a non-issue because the wrapper functions now allow compilers to check for overflows. Change-Id: I975bf8152fc961767f0292bff4a03aecd8c65f56 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51886 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03nb/intel/common: Drop deprecated fixed BAR accessorsAngel Pons
Now that all code has been switched to make use of the new accessors, the old ones can be dropped. Follow-ups will clean up bitwise accessors. Change-Id: Ib4cb24ca71f3c3717ea50d147ddca74aaf0288fa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-03nb/intel/haswell: Move PEG registers to a separate headerAngel Pons
To keep the "main" haswell.h header short and simple, move PEG register definitions into a separate file, as done with most other registers. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ibfca00456115a4a0c861dd6738605214a7d43fd9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51891 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02nb/intel/common: Turn `*bar_{read,write}*` macros into functionsAngel Pons
These accessors were defined as macros in order to allow verifying the patches that replaced the accessors using BUILD_TIMELESS=1. Now that all replacement is done, turn the new accessors into static functions to let the compiler perform overflow checks on the arguments. Change-Id: Iaa2ba208fba11c4a00f2b8a05eb1129a32c6c092 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52816 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02nb/intel/haswell: Uniformize include guardsAngel Pons
Remove leading and trailing underscores and change `RAMINIT_H` to be more consistent with other headers. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: Ie20fcaa0f9393eb0a34054eda53b9bade63cc0d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51890 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02nb/intel/haswell: Clean up haswell.h headerAngel Pons
Drop unused chipset type macros, remove unnecessary guards and reorganize contents so that headers can be included at the top. Also drop the inclusion from ASL, as it is no longer necessary. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I6fcc0d428d0fdbf410bcbeb6ae4809870b7b498f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51889 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26haswell/broadwell: Replace remaining MCHBAR accessorsAngel Pons
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 and Purism Librem 13 v1 remain identical. Change-Id: I74b633fb0b012304b5b4bd943272ed82dcb6f7d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52468 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 20:39:22 +0000