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XMP profiles can have a restriction on max supported DIMMs per channel,
but many configurations work with more DIMMs.
This is relevant on mainboards with 2 DIMM slots per channel (usually 4
in total). Populating both slots with DIMMs that support XMP profiles only
with 1 DIMM per channel turns off said XMP profiles.
TEST=On a system with two DIMM slots per channel populate both slots on
one channel and ensure that DIMMs run with XMP profiles enabled.
Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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DRAM Controller is always 00.0. No need to check its PCI ID.
Change-Id: I9c5f3e5658905e464491579f8da01aa6a03bd3b7
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I1899dbe9498a0cc83b65b4bc1c6c0a555637fd05
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Port the ACPI opregion implementation that resides in
drivers/intel/gma to older platforms.
It allows to include a vbt.bin and allows GNU/Linux to load the
opregion as ASLS is being set.
Windows' Intel will likely ignore it as it relies on legacy VBIOS
to be loaded at 0xc0000.
Tested successfully on DG43GT (x4x) with vbt.bin,
with X200 (gm45) with vendor option rom and
D945GCLF (i945) with fake vbt.
Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The scramble seed intended for CH1 were written to the regs of CH0.
Write the scramble seed for CH1 at the correct offset.
TESTED on Lenovo T430, HP 2760P, Asrock B75PRO3-M.
Change-Id: I3778947e96b3298c38e6d5b74988e617e1ffea7b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Iru Cai <mytbk920423@gmail.com>
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This code path was only triggered in one corner case: GFX UMA set to
48MiB. It created a hole below UMA to save MTRRs. But, this hole was
never accounted for when calculating cbmem_top(). Instead of trying
to fix it, remove it, it's not worth the trouble.
TEST=Booted lenovo/x200 with all available CMOS gfx_uma_size settings.
Change-Id: I3f4ceec4224d86113be9bfa3ce4759bed584640d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Remove no-op statements and code-rephrasing comments, apply some cosmetic
changes to improve readability.
Change-Id: I124a6bc338c2589fab66ca91bf53139b4413d10b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add debug messages for SPD probing.
Change-Id: I722102b7981781b88cdc4877f698294eb719ff32
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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SPD decoding problems are no longer a good method for detecting if i2c
byte read failed, since the return value of i2c_block_read is checked.
Change-Id: I230aa22964c452cf28a9370c927b82c57e39cc62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Needed for coreboot spi driver.
Change-Id: I01059c8cbdc6a002dfd75b6da3a629811b137702
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: If6cf47e4a87cf008d51f65fd1c1c79392c4b2786
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21619
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This simplifies computing dram timings a lot.
This removes computation of rank size based on columns, rows,
banks,... and uses the information in SPD byte 31. The result of this
is that dimms with multiple asymmetric ranks are not supported
anymore. These however are very rare and most likely never tested on
this platform.
This also uses i2c block read instead of byte read to speed up the
raminit. The result is less time is being spend reading SPDs.
It still keeps smbus read byte as a backup if i2c block read were to
fail.
Change-Id: I97c93939d11807752797785dd88c70b43a236ee3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I270d17a2eff2c6664bf936425a6ed344be3feabe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/21524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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There's no reason to mutate the struct device when determining
the ACPI name for a device. Adjust the function pointer
signature and the respective implementations to use const
struct device.
Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Use macro instead of numbers
Change-Id: Ife1aff0a5cf311881b3a11533b71a74c518a633f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/21472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Implement cbmem_top() required for cbmem support in romstage.
Boot tested on asus/p2b-ls. Boards to move to this setup in
followup patches.
Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20977
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Even with the watchdog disabled, these bits influence other hardware
blocks (e.g. SECOND_TO_STS stops SMBus block transfers, possibly yet
before they started).
Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Inspired by gm45 code, which sets this value the same way.
Some values for tRD on 800 and 1067MHz FSB were set wrong because the
CAS/Freq selection was wrong. CAS was often selected to low and when
fixing CAS this results in tRD being too high, due to an incorrect
lookup table which caused instability.
PASSED memtest86+ during 10h+ on 1067MHZ fsb with 667MHz ddr2, CAS 5
on GA-945GCM-S2L.
Change-Id: I8002daf25b7603131b78b01075f43fd23747dd94
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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We set the SPI lockdown in BS_POST_DEVICE (dev_finalize()) on many plat-
forms now. The SPI controller is initialized at start of BS_DEV_INIT
(dev_initialize()).
The SPI lockdown usually shouldn't be a problem but the SPI driver imple-
mentation lacks full support for the locked interface. Also, some options
exist to lock all flash regions read-only until the next reboot.
Change-Id: Ifda826ae2bb28adcce8dda8e2bb16dc38fe0fe9e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
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Without this remapping code enabled, the system fails to boot properly
if the amount of ram inserted is larger than 4G minus the mmio
space (hardcoded to 1G here).
Change-Id: I02e7ceed0cd9db7eb7182481b6989f80cef31ee5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Fix dump_pci_device() broken by commit 65b72ab5 (Drop print_ implementation
from non-romcc boards) in 2015 (!) where only one in 16 bytes were being
dumped.
Also remove the #if made redundant by commit aef8542 (Compile debug.c
only if CONFIG_DEBUG_RAM_SETUP) as this whole file is only compiled in
that case.
Also clean up headers that were included twice.
Change-Id: I60e272b29417039feb15540e49d7300f86e5ed21
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Some of these will move to EARLY_CBMEM_INIT.
Change-Id: Ia969e30ad7097860180bd047eaf81859a42a747c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
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This problem was introduced in:
12a4e98cea nb/intel/pineview/raminit: Refactor timings selection
Change-Id: Iace3dabb8546d7a721ef13526ba02522dc712fdd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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A small typo in the dll setting code prevented this combination from
booting.
TESTED on ga-g41m-es2l with 800MHz FSB CPU and 667MHz ddr2
Change-Id: Ib013471773c20336ba0902b7f328bfb6ef970747
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Moves receive enable calibration to a separate file to lighten
raminit.c a bit.
Receive enable calibration is quite similar to gm45 so it reuses some
of its function names.
The functional changes are:
* the minimum coarse is now reset for each channel;
* on the second fine search for DQS high, TAP overflow is handled by
increasing medium;
* start coarse at CAS + 1 instead of CAS - 1. Other Intel northbridges
do the same and the results are more in line with register dumps
from vendor bios.
These might improve stability.
TESTED on ga-g41m-es2l
Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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... is enabled. Otherwise we are compiling an effectively
empty file.
Change-Id: I4e3d982066d1fa66a3da5f37e278ec7fd5bb1ea8
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
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The S3 resume path is broken on current Linux (4.11.3) and maybe
on older kernel, too.
Don't run the native graphics init when on S3 resume to fix it.
Tested on Lenovo T430.
Change-Id: Ifad145c86c2e8f019c507f97c889b70b7aa49882
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This allows the use of the native VGA init on boards featuring DVI-I
ports. Digital output is not supported.
Change-Id: I11a4dd68746e06c7e27ecf3e765bdd0d8cf40515
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Migrate opregion code from northbridge/intel/common to
drivers/intel/gma in preparation for consolidation with
soc/intel/common opregion code. Rename init_igd_opregion()
for clarity and disambiguation with other implementations.
Change-Id: I2d0bae98f04dbe7e896ca34e15f24d29b6aa2ed6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add a new Kconfig option to ignore memory fuses that limit the
maximum DRAM frequency to be used. The option is disabled by
default and should only enabled by experienced users as it
might decrease system stability or prevent a successful RAM
training.
Remove conflicting devicetree settings.
Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nicola Corna <nicola@corna.info>
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Change-Id: I885b6bd9f5be6b4e3696a530016123a3e81c4b10
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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All Intel southbridges implement the same SMBus functions.
This patch replaces all these similar and mostly identical
implementations with a common file.
This also makes i2c block read available to all those southbridges.
If the northbridge has to read a lot of SPD bytes sequentially, using
this function can reduce the time being spent to read SPD five-fold.
Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Sync map_oprom_vendev() and autoport with the list of PCI ids in the
`gma.c` driver, remove one obsolete Kconfig default override.
Change-Id: I12f24f415b695c516fbb947114e09c873af2e439
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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The newline lint check just went in, and immediately broke the build
due to a commit that went in earlier today.
This fixes the build.
Change-Id: Ic4ba8ce0c8085861bc6c654afdee3fea9f4621fc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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There are 4 routines used in RAM init that most if not all
i440bx mainboards call in the same order. Implements a single
RAM init routine for them to allow for future consolidation.
Boards to be changed to use this one routine in a future change.
Change-Id: Ib553b07b117de12b7982586bce0f9355f55013a0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This move makes the NB macro more widely available,
in preparation for implementing get_top_of_ram().
Change-Id: Icd8e82cfdfdccb662b2139d0e5d1d5af72cbae7f
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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This does the following:
* Clarify that settings are set to the same value for each rank;
* Allows to program coarse
* Fix some style issues like white spaces between arithmetic
operators.
Change-Id: I3a9e28cfec915a0bb15789c23bea259f621b5096
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This does not use loops to compute timings but uses DIV_ROUND_UP.
Another thing affected by this patch are minimum timings. Presumably
those only need to be guarded against on DDR3. With this change
timings are set up like vendor (with tWTR below previous minimum)
TESTED on Intel D510MO
Change-Id: Ia374f26e5bbb8b90d90c24ae6c20412ba53bd7b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: Ic7132cd1848a75043d10f32ac5d0e6b45d2e0fe4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: I1944fcca91ee1a0ad8df5c8b6f402e907de5e78f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: I772d680774890c32ca6dc9b1e2143b3ab3bf6513
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: Ifc921d7aa2d5b771fc4eaf3ec776c3a13f5496eb
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add and use new interface to set and get GNVS' ASLB register.
To be used by Intel's gma driver to set ASLB at ACPI table
creation and to get ASLB on S3 resume.
Change-Id: If30c6b2270069783b0892774802f47406404da5f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use new GMA driver method to set ASLS.
Change-Id: I872ff86a778497df76ad7f9b1b6910c4e7c5941f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: Id1ed2252ce3ed052730dd10b24c453c34c2ab4ff
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
DIMMB's DDR width is in bit 20, not bit 19.
Change-Id: I48866d9243c2a576a02519724429801ae47c5644
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.
Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
DISPPLANE_BGRX888 defined in drivers/intel/gma/i915_reg.h
included in i915.h file
Change-Id: I4e9414f39a29e4eac7e325672ce6520a5654d3bc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: Ic01bbae9acaabaade777db52825aa80d25fc5961
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The ALSB gnvs variable is used to load the OpRegion memory
address into the ASLS register on the S3 resume path, and must
therefore first be set on the normal boot path.
This patch brings Haswell in line with SNB/IVB/Nehalem, which
already save the OpRegion address in ASLB.
Change-Id: Ie062cbfe7e7f60c2a4e2b9111f6b6da87ced7a39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Needed to generate cpu entries.
Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Code checked manually
Change-Id: Idf86546ddda4fa2b4b96f0b703c03af9931c757d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Fill in acpi_name to return proper ACPI names. To be used with
SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
GFX0 is used in drivers/intel/gma/acpi/pch.asl.
MCHC is used in nb/intel/sandybridge/acpi/hostbridge.asl.
Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
On boards that are able to take two DIMMs per channel the
command rate should be 2T. It is possible to use 1T with
load reduced "1T" DIMMs, but it's not clear how to detect
those DIMMs. Raminit might fail for those who do not have
such DIMMS installed.
Hardcode command rate of 2T to make sure raminit works on
dual DIMM per channel boards (currently only desktop boards).
The command rate of 1T is still tested if only 1 DIMM per
channel is present.
Will decrease performance on quad slot mainboards, if two DIMMs
are installed in one channel and previously 1T have been selected.
Tested on ASRock B75 Pro3-M.
Change-Id: I029d01092fd0e11390cebcd94ca6f23bf0ee2cab
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Maybe we could go on, but cbmem_add() failing is a very bad sign.
Should fix coverity CID 1376384 (Null pointer dereferences
(NULL_RETURNS)).
Change-Id: I330cee6db3540c6a9c408d56da43105de5d075f7
Found-by: Coverity Scan #1376384
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20280
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
|
|
These delays, adding up to 600 ms, don’t seem to be needed, so remove
them.
TESTED on d510mo, boots fine without.
Change-Id: If089d6677fe95b086eeb00540acfbb66fa2e1c47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
|
|
Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older
Haswell MRC binary doesn't populate the pei_data struct with
all the info needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Use common init_igd_opregion method and remove duplicated code in
acpi.c.
Change-Id: I811e8bd2be68813321dc4581af02e1c21b0da076
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Add method gma_write_acpi_tables.
No need to update GNVS as it doesn't have ASLB.
Change-Id: Ia138cfde2271a298c36b85e999ff69f0f211ba11
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Use common init_igd_opregion method.
Change-Id: Ia10a28d05b611a59f787b53f9736b3b76a19ea4a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Use common init_igd_opregion method.
Change-Id: Ic8a85d1373f04814b4460cce377d6e096bcdc349
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Too low gfx_uma_size can result in problems if the framebuffer
does not fit.
This partially reverts: 7afcfe0 "gm45: enable setting all vram sizes
from cmos"
Change-Id: I485d24198cb784db5d2cfce0a8646e861a4a1695
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Also changes the arguments of some functions to const.
This reduces romstage size by a whopping 1009 bytes.
Change-Id: I054504412524b7be19d98081097843b61bc0c459
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
|
|
Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
The previous code seemed weird and tried to check if its selected
value is supported three times.
This also lower the clock if a selected frequency does not result in a
supported CAS number.
Change-Id: I1df20a0a723dc515686a766ad1b0567d815f6e89
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
The previous code seemed weird and tried to check if its selected
value is supported three times.
This also lower the clock if a selected frequency does not result in a
supported CAS number.
Change-Id: I97244bc3940813c5a5fcbd770d71cca76d21fcae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Use common init_igd_opregion method.
Change-Id: Ie70a49fd532b7ad7679dc558cc4a019a273a0602
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Copy Haswell's init_igd_opregion to common folder.
Remove platform specific code.
Will replace all Intel NB implementations.
Change-Id: I14dfb5986df264ffd71183a159f98b79e8e3230e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Switch from lapic to tsc.
Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.
Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.
Tested on Lenovo T430.
Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Provide all gfx init methods as a Kconfig `choice`. This elimates the
option to select native gfx init along with running a Video BIOS. It's
been only theoretically useful in one corner case: Hybrid graphics
where only one controller is supported by native gfx init. Though I
suppose in that case it's fair to assume that one would use SeaBIOS to
run the VBIOS.
For the case that we want the payload to initialize graphics or no
pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the
choice. If multiple options are available, the default is chosen as
follows:
* NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS,
* VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS,
* NATIVE_VGA_INIT, if we don't add a Video BIOS.
As a side effect, libgfxinit is now an independent choice.
Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the
reference clock can be 100Mhz.
Decode the register and use the reference clock to calculate
the selected DDR frequency.
Tested on Lenovo T430.
Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put
it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are
two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt
and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for
`HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model
that with additional symbols.
Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers
that support a linear framebuffer. Some related settings moved to the
drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are
hardcoded.
Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.
Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The deprecated LATE_CBMEM_INIT function is renamed:
set_top_of_ram -> set_late_cbmem_top
Obscure term top_of_ram is replaced:
backup_top_of_ram -> backup_top_of_low_cacheable
get_top_of_ram -> restore_top_of_low_cacheable
New function that always resolves to CBMEM top boundary, with
or without SMM, is named restore_cbmem_top().
Change-Id: I61d20f94840ad61e9fd55976e5aa8c27040b8fb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
|
|
It could end up not initialized which causes it not to build with
clang.
Change-Id: I3be9477d836123aaa87c9bebb41c1ec34689a771
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I3cd5e99b9954a68837de85b49b4389b668e00cf4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
This makes the code more readable since it avoids messing with two
dimensional arrays and needing remember what the indices mean.
Also introduces an unused coarse element which is 0 for all default
DLL settings on DDR2.
Change-Id: I28377d2d15d0e6a0d12545b837d6369e0dc26b92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
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Hides JEDEC steps using the RAM_SPEW macro.
Also hides a hexdump of SPDs.
Change-Id: Ie2b484cf1f1d296823df0473e852d9d07ca20246
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This improves readability.
Change-Id: Ib4387a4f4092053dab273191a73edb0ef31a79f6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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It is not really known why there is such a long delay, but it works
fine without it.
TESTED on ga-g41m-es2l.
Change-Id: Idff5b978bbf161f8520d8000848e7b11c98c3945
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19514
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Hide device 4 and device 7 if disabled.
Allows devicetree settings to take effect.
Tested on Lenovo T430.
Change-Id: I64a19e2bbdb1640e1d732f6e4486f73cbb0bda81
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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A left-over from 5e3cb72a71 (nb/x4x: Do not enable IGD when not
supported). Should fix coverity issue 1375009. Remove a redundant
line that uses the variable `gfxsize` out of its scope and move the
variable declaration. Make sure the variable is always initialized,
drop unneeded error-handling for `get_option()` and sanitize the
read value instead.
Change-Id: Iee2beda30d8c74df0f412622c3ff3357819e386b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19680
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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`cardF[n]` should indicate whether the DIMM in channel n is of
raw card type F. However, `cardF[1]` was initialised with the
value meant for `cardF[0]`. This patch results in the correct
initialisation of `cardF`.
Tested on a Lenovo T400 containing two DIMMs: one of raw card
type F and the other of raw card type B. Before the patch, the
system would not boot. After the patch, the system boots with all
of the memory functional.
Change-Id: I7409df0b8c67d7efbdadae39dc718c8df7a92552
Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Reviewed-on: https://review.coreboot.org/19652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This results in raminit_receive_enable_calibration.c producing
no errors or warnings with checkpatch.
The issues fixed are:
ERROR: that open brace { should be on the previous line
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
Tested by compiling after making the changes.
Change-Id: I8d2f4f1fe2f17aa44c0a7090c178eee418defe78
Signed-off-by: Tristan Corrick <tristancorrick86@gmail.com>
Reviewed-on: https://review.coreboot.org/19651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Currently only one board uses this northbridge in coreboot but some
patches are pending to add more.
Change-Id: If035e442d1a23674667f46a07b44c4f2b81be48c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I2308b069b8f2c601254169bcb6a34442c537a311
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I15550b1cc1a7ccfecba68a46ab2acaee820575b9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Is only present on the P45 subtype of chipset.
Change-Id: I6b138db6654c83c40b5ca4b65d6ccd51ad4277fa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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According to "Intel ® 4 Series Chipset Family datasheet" in the
description about GGC and DEVEN, CAPID0 bit46 is said to reflect the
presence of an internal graphic device. This would allow the P43 and
P45 chipset variants to work.
Change-Id: Icdaa2862f82000de6d51278098365c63b7719f7f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18515
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The NGI writes to legacy VGA registers which should not happen when
VGA cycles are assigned to a different device.
TESTED on ga-g41m-es2l
Change-Id: I0a03e35c0d7f2532edd6cc5e62d1cf07dab57f60
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This disables VGA cycles on IGD when an external VGA device is
found. This allows PCI or PCIe devices to be the 'main' VGA device if
found, while the IGD is still available.
TESTED on ga-g41m-es2l: SeaBIOS shows payload on external GPU while
linux (4.10) can use both as a framebuffer simultaneously without any
extra configuration.
Change-Id: I74890918feb0f1ff6b971c4aaa96f1f7b75266ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Computes TSEG size dynamically.
Changes the size of legacy hole to match other Intel northbirdges.
Refactor this a little by needing one less variable.
Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This code ought not to run if ME is disabled. It also prohibits
writing to some GMCH regs like GGC bit1.
Intel ® 4 Series Chipset Family datasheet refers to this as
"ME stolen Memory lock" without actually describing this
functionality.
Change-Id: Iaa8646e535e13c44c010ccd434a5af954cf7dfbc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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