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2008-12-09Add (parts of the) support for multiple DIMMs on the Intel 440BX chipset.Uwe Hermann
This is tested on hardware with four 128MB DIMMs and works ok, _iff_ you also fix additional registers (e.g. DRB, RPS, ...) for your setup. This requirement will be eliminated in another upcoming patch (i.e. all of the required settings will be auto-detected). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-27Remove the unnecessary memctrl[] indirection, 440BX only has oneUwe Hermann
memory controller. Also, drop some unused '#if 0' code. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-21i810: Add support for multiple DIMMs, both single-sided and double-sided,Elia Yehuda
as well as most (all?) combinations thereof. Drop some unused code, the unused row_offset variable, and obsolete comments. Also, fix a typo (thanks to Stefan Reinauer for noticing). This is tested on the MSI MS-6178 with a number of different DIMM combinations and so far all of them worked fine. Signed-off-by: Elia Yehuda <z4ziggy@gmail.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-20Get rid of the unnecessary indirection by 'struct mem_controller' for theUwe Hermann
Intel 810 chipset (and all boards using it). This isn't required for this chipset as there's only one memory controller. This also helps a lot with romcc register usage, you should see the dreaded "too few registers" less often. Build-tested with all three boards using the Intel 810 chipset. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-18i810: Add some more comments, and especially add a list of tested BUFF_SCUwe Hermann
values for different DIMM configurations. This should be converted to a table or code later on and actually be used for BUFF_SC. Many thanks to Elia Yehuda <z4ziggy@gmail.com> for testing and collecting the table entries. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-11Thanks to Uwe Hermann for spotting this typo.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-10Merge some parts of the i945 review (trivial):Stefan Reinauer
* fix \r\n occurence in i945 code * drop early TOLUD write * fix 16bit BCTRL1 access Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-09i945.h: Add some more comments, align data for better readability (trivial).Uwe Hermann
Also, add missing C1DRA2 #define (as per public datasheet). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines.Uwe Hermann
Build-tested on kontron_986lcd_m. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29i945/ICH7: Use #defines from pci_ids.h (trivial).Uwe Hermann
Build-tested with the kontron/986lcd-m target. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29Support for the Intel 945 northbridge.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-12Drop tons of duplicated debug.c files, move common file toUwe Hermann
lib/debug.c and use that one. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-01The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots ofCarl-Daniel Hailfinger
code to use it. That makes the code more readable and also less error-prone. Abuild tested. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-30A duplicate register address is incremented in table register_values.Mats Erik Andersson
A trivial fix to correct the address of the high byte in SDRAMC. Thus the leadoff timing IPDLT will be correctly referenced. Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-09-24Support for the memory controller and PCIe interface of the IntelEd Swierk
EP80579 Integrated Processor (codename "Tolapai"). The memory controller code supports only 64-bit-wide DIMMs with x8 devices and ECC. It has been tested on a development board using a single Micron MT9HTF6472PY-667D2 DIMM. Your mileage will definitely vary with other DIMMs. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-28Eric Biederman believes that he and Tom Zimmerman of the defunctEd Swierk
LinuxNetworx own the copyright for the Intel e7520, e7525 and 3100 raminit code. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25This patch adds PCI device IDs for the Intel EP80579 Integrated Processor,Ed Swierk
and renames some existing macros for clarity. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-06-22This patch allows support for multiple so-dimms, single or double sided.Joseph Smith
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-05-15This patch allows the RCA RM4100 to reboot. Upon rebooting in auto.c it ↵Joseph Smith
detects if the memory is already initialized, if so it issues a hard reset through the southbridge. Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-16This patch implements support for the Intel 3100 integrated ↵Ed Swierk
northbridge and RAM controller. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-03-09Initial support for the Intel 82830 northbridge and RCA RM4100 board.Joseph Smith
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3129 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Rename almost all occurences of LinuxBIOS to coreboot. Stefan Reinauer
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-01-18Please bear with me - another rename checkin. This qualifies as trivial, noStefan Reinauer
code is changed. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-27Drop duplicated and unneeded #defines from some northbridges (trivial).Uwe Hermann
This is generic PCI stuff, not nothbridge-specific in any way. The respective #defines are already present in src/include/device/pci_def.h. Abuild-tested, so shouldn't break anything. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24Ever wondered where those "setting incorrect section attributes forStefan Reinauer
rodata.pci_driver" warnings are coming from? We were packing those structures into a read-only segment, but forgot to mark them const. Despite its size, this is a fairly trivial patch created by a simple search/replace Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-19Various minor cosmetics and coding style fixes (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-19This patch fixes up a couple mistakes I made with the i82810 and mew-vw to makeCorey Osgood
the system boot to a command line. This patch comments out the code to set up the vga framebuffer to allow the system to boot, without this fix the system hangs during elfboot. The only line that is absolutely necessary to change is the SMRAM setup, however I've commented out all vga setup to make it very obvious to both the kernel/payload and anyone looking at the code that vga isn't currently working. This setup might also be better handled in northbridge.c, if it doesn't need to be done before ram init, yet another reason to comment it all. In the future, LinuxBIOS needs to be told that the graphics memory area, 1mb or 512kb (at the user or developer's option), is reserved for the onchip vga, but I'm not sure if it's taken at the top or bottom of the memory, yet. LB may also need to set a base address for the AGP aperture and/or be told that range is reserved as well, whether this was originally the job of the system bios or vga bios is still a mystery. It also corrects the number of entries in irq_tables.c, without this fix the kernel would probably complain and hang due to unmapped IRQs. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14Add initial support for the Intel 82810 northbridge.Corey Osgood
Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-07Minor tweaks in the 440BX RAM init code (trivial).Uwe Hermann
Still hardcoded for Tyan S1846. This slightly increases performance, but it's still pretty horrible. Some RAM settings are causing a dramatically slow system (confirmed by comparing memtest performance results of the proprietary BIOS and our code). Haven't found the problem, yet. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-28Lower the RAM init delays we use on the Intel 440BX.Uwe Hermann
As per JEDEC, we should wait 200us until voltages and clocks are stable. Then apply NOPs for 200 clock cycles (for simplicity we use 200us here). All other delays are so low that we get away with just waiting 1us. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-27Various 440BX and Tyan S1846 related minor changes and fixes (trivial):Uwe Hermann
- Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's available on all boards, regardless of what DIMMs you use. Tested on the Tyan S1846, works fine. - Properly set the PAM registers to allow the region from 768 KB - 1 MB to be used as normal RAM (required for the above). - Document all of this properly. Add/improve other documentation, too. - Simplify and document code in northbridge.c. - Cosmetics and coding style. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fixup the 440BX northbridge.c (self-ack as this wasn't working anyway).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-10Fixed a bug within the 440BX RAM size calculation. Since the DRB valuesCeri Coburn
on the 440BX are 8 MB units we need to shift left by 13 to get it into KB. Signed-off-by: Ceri Coburn <ceri.coburn@gmail.com> Signed-off-by: Roger Zauner <roger@eskimo.com> Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-05-04Cosmetics (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-30Fix typo: s/PRINT_DEBUG_/PRINT_DEBUG/ (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-04-01Initial Intel 440BX RAM initialization framework.Uwe Hermann
This does _not_ fully work, yet. You will _not_ be able to boot any payload with this code, yet. Add missing license headers. Base the northbridge.c file on the Intel 855PM version, that comes closer to what we want. The raminit.c file is written from scratch and hardcodes several values for now. This needs to be fixed later by reading the correct values via SPD. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-30Add convenience macros PAM0..PAM6 (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2511 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-22Update of the src/include/spd.h file with the following improvements:Uwe Hermann
* Added information on the relevant datasheet(s) and where to get them. * Added missing #defines for some other config bytes. * Documented all config bytes a bit better. * Renamed some #defines to hopefully make their names clearer. (closes #38) Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2506 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-11Add missing bracket in comment, and fix whitespace (trivial).Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-10Add an include file which contains the register definitions for theUwe Hermann
Intel 440BX northbridge (Closes #39). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Richard Smith <smithbone@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-05Use the canonical name of the vendors/devices and theUwe Hermann
same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@linuxbios.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-27svn mv src/northbridge/intel/E7520 src/northbridge/intel/e7520Uwe Hermann
svn mv src/northbridge/intel/E7525 src/northbridge/intel/e7525 Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-10-27Rename E7520 to e7520, and E7525 to e7525 in the code. The next commitUwe Hermann
will then rename the E7520 and E7525 directories respectively. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-08-23Uwe Hermann:Stefan Reinauer
here's a patch which replaces all DOS newlines with Unix newlines, and removes some useless $Rev$, $Id$, and $Header$ tags. (part 1) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-29- Add support _framework_ for the Asus p2b. Richard Smith
- New superIO winbond/w83977tf - Add single memory controller SBbus debug routine into a file private to the i440bx This adds support the start of support for an Asus p2b mainboard. Current limitations are the same as for the Bitworks IMS board. Reads from the SMbus don't work. Moving dump_spd_registers() into its own private copy solves the problem of having to go hack on the version that included in src/sdram to only do one memory controller. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-24add framework for i440bx chipsetRichard Smith
add support for NSC pc87351 SuperIO add Bitworks/IMS manboard config This is a very basic framework for the i440bx chipset and the Bitworks IMS board that uses it. Most things are structure only. Known issues: - SMbus reads to the RAM SPD come back all zero. - dump_spd_registers() is commented out since it breaks with the default setting of generic_dump_spd.c where it wants 2 memory controllers. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-05-26fix two mainboards that have been broken by someone who does not use abuild.shStefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2313 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-28Make #defined constants more descriptive.Steven J. Magnani
This was missed in the checkin of raminit.c changes. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-10-05Updating FSF address in the code.Stefan Reinauer
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-26* Added support for "fast" (64-clock) refreshSteven J. Magnani
* Added code to support remap window for 3 - 4 GB systems * Fixed premature configuration of true row boundaries that resulted in some sections of DRAM not receiving JEDEC commands (see http://openbios.org/pipermail/linuxbios/2005-June/011752.html). * Redefined RCOMP_MMIO so that RCOMP registers can be configured on systems where A20M# is asserted. * Disabled subsystem (vendor) ID configuration * #ifdef'd out suspicious looking code (see http://openbios.org/pipermail/linuxbios/2005-June/011759.html) * Added optional run-time checking of dual-channel compatibility of installed DIMMs * Move JEDEC SPD and SDRAM definitions into reusable #include files git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-13Moved E7501-specific definitions here from raminit.Steven J. Magnani
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08eric patchYinghai Lu
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-06Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51arch import user (historical)
Creator: Yinghai Lu <yhlu@tyan.com> cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-28fixes to make adl855pc compile.Ronald G. Minnich
fixes to emulator. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-18- First stab at getting the ppc ports building and working.Eric Biederman
- The sandpointx3+altimus has been consolidated into one directory for now. - Added support for having different versions of the pci access functions on a per bus basis if needed. Hopefully I have not broken something inadvertently. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-11in loglevel.h, if ASM_CONSOLE_LOGLEVEL is defined, don't try to set it.Ronald G. Minnich
Set adl855pc ROM_SIZE to 1M Other minor debug prints until we get this fixed. We're almost as far along as we were before the Change :-) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-10- Remove e7501 root_complexEric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-10adl855pc supportRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05CONFIG_CHIP_NAME to control config chip.h without .nameYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04- Update abuild.sh so it will rebuild successfull buildsEric Biederman
- Move pci_set_method out of hardwaremain.c - Re-add debugging name field but only include the CONFIG_CHIP_NAME is enabled. All instances are now wrapped in CHIP_NAME - Many minor cleanups so most ports build. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02*** empty log message ***Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27sizeram removal/conversion.Eric Biederman
- mem.h and sizeram.h and all includes killed because the are no longer needed. - linuxbios_table.c updated to directly look at the device tree for occupied memory areas. - first very incomplete stab a converting the ppc code to work with the dynamic device tree - Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources). - First stab at Pentium-M support - add part/init_timer.h making init_timer conditional until there is a better way of handling it. - Converted all of the x86 sizeram to northbridge set_resources functions. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27- kill the broken and duplicate 855pm directory. Hopefully I have keptEric Biederman
the least broken one. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25ops and tscYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25s2735 minor changesYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23- For now use port 0x80 based delays in for the e7501 memory initialization.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23- Update e7501 northbridge.c to work in the new structure.Eric Biederman
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23*** empty log message ***Yinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21- Bump the LinuxBIOS major versionEric Biederman
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16- First stab at running linuxbios without the old static device tree.Eric Biederman
Things are close but not quite there yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06f'ing thing still won't work.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-30mods for i855pm that don't seem too wrong. ha!Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-28add support for ICH4. more i955pm stuff.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-30more fixes.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-26just a few changes before we hit the big fun.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-25more updates for 855Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-24stupid ron! need to start names with a letter.Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-08-23adding 855pmRonald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-07-01Intel E7501 P64H2 ICH5R supportYinghai Lu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1616 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-06 16:36:27 +0000