summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
AgeCommit message (Expand)Author
2018-06-20nb/intel/e7505: Leave ROM as un-cacheable in postcarKyösti Mälkki
2018-06-17nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki
2018-06-17nb/intel/i440bx: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
2018-06-17cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki
2018-06-17nb/intel/nehalem: Fix DEVEN definesPatrick Rudolph
2018-06-17nb/intel/x4x: Issue a hard reset with empty MRC cache on warm resetArthur Heymans
2018-06-14cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans
2018-06-14nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xceElyes HAOUAS
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
2018-06-14nb/intel/x4x: Work around a quirkArthur Heymans
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
2018-06-07nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans
2018-06-07nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans
2018-06-07nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans
2018-06-06intel/e7505: Remove ROMCC workaroundKyösti Mälkki
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
2018-06-06arch/x86: Flag platforms without RELOCATABLE_RAMSTAGEKyösti Mälkki
2018-06-05cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05cpu/intel/model_2065x: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05cpu/intel/model_206ax: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05nb/intel/gm45: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05nb/intel/pineview: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05nb/intel/i945: Switch to POSTCAR_STAGEArthur Heymans
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
2018-06-04intel/i440bx: Drop tests for LATE_CBMEM_INITKyösti Mälkki
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
2018-06-04nb/intel: Use postcar_frame_add_romcache()Nico Huber
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
2018-06-02intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGEKyösti Mälkki
2018-06-02intel/e7505: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
2018-06-02intel/e7505: Assume AGP slot disabledKyösti Mälkki
2018-06-02aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INITKyösti Mälkki
2018-06-02intel/e7505: Fix domain resourcesKyösti Mälkki
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
2018-05-29src/northbridge: Add and update license headersMartin Roth
2018-05-24nb/intel/fsp_sandybridge: Fix lost const qualifier on 'device_t'Elyes HAOUAS
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
2018-05-24nb/intel/sandybridge: Get rid of device_tElyes HAOUAS
2018-05-21nb/intel/nehalem: Fix smashed stack in romstageMatthias Gazzari
2018-05-18nb/common/intel: Remove the mrc cache codeArthur Heymans
2018-05-18nb/intel/nehalem: Use the common mrc cache driverArthur Heymans
2018-05-18nb/intel/e7505: Get rid of device_tElyes HAOUAS
2018-05-18nb/intel/haswell: Get rid of device_tElyes HAOUAS
2018-05-17nb/intel/nehalem: Add ACPI pathPatrick Rudolph
2018-05-14nb/intel/fsp_sandybridge: Get rid of device_tElyes HAOUAS
2018-05-14nb/intel/i945/raminit.c: Remove not necessary braces {}Elyes HAOUAS
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
2018-05-14nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans
2018-05-11nb/intel/i945/bootblock.c: Correct commentElyes HAOUAS
2018-05-11nb/intel/i440bx: Get rid of device_tElyes HAOUAS
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
2018-05-01nb/intel/x4x: Change memory layout to improve MTRRArthur Heymans
2018-05-01nb/intel/x4x: Fix programming CxDRBArthur Heymans
2018-05-01nb/intel/x4x: Implement both read and write trainingArthur Heymans
2018-05-01Fix freeze during chipset lockdown on NehalemMatthias Gazzari
2018-04-30nb/intel/fsp_rangeley: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/i440: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/pineview: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/sandybridge: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/nehalem: Get rid of device_tElyes HAOUAS
2018-04-30nb/x4x: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/i945: Get rid of device_tElyes HAOUAS
2018-04-30nb/intel/gm45: Get rid of device_tElyes HAOUAS
2018-04-28nb/intel/x4x: Fix computing page_sizeArthur Heymans
2018-04-28nb/intel/i945/gma: Skip native VGA init for ACPI S3 resumePaul Menzel
2018-04-28nb/intel/i945/gma: Factor out code to new `gma_ngi()`Paul Menzel
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
2018-04-17nb/intel/x4x/rcven.c: Change the verbosity of some messagesArthur Heymans
2018-04-17nb/intel/x4x: Add a convenient macro to loop over bytelanesArthur Heymans
2018-04-17nb/intel/x4x: Clarify the raminit memory mappingArthur Heymans
2018-04-17nb/intel/x4x: Refactor setting default dll settingsArthur Heymans
2018-04-17nb/intel/x4x: Use SPI flash to cache raminit resultsArthur Heymans
2018-04-16nb/intel/i945/gma: Log native graphics init in level INFOPaul Menzel
2018-04-16nb/intel/i945/gma: Fix aligment of equal signPaul Menzel
2018-04-16nb/intel/sandybridge: support more XMP timingsDan Elkouby
2018-04-13nb/intel/sandybridge/peg: Add PEG driver stubPatrick Rudolph
2018-04-11Revert "model_206ax: Use parallel MP init"Arthur Heymans
2018-04-11model_206ax: Use parallel MP initArthur Heymans
2018-04-10cpu/intel/sandybridge: Put stage cache into TSEGArthur Heymans
2018-04-09intel/nehalem post-car: Use postcar_frame for MTRR setupKyösti Mälkki
2018-04-04nb/intel/gm45/raminit: Use CxDRT*_MCHBAR instead of magic numbersJonathan Neuschäfer
2018-03-28nb/intel/gm45: Allocate a 8M TSEG regionArthur Heymans
2018-03-08nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APICMatt DeVillier
2018-03-08nb/intel/haswell: Generate ACPI DMAR tableMatt DeVillier
2018-03-03nb/intel/i945/gma: Log configured VGA modePaul Menzel
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 14:53:18 +0000