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2016-09-20northbridge/intel/e7505/debug.c: Improve code formattingElyes HAOUAS
Change-Id: I63f58d95fa01b1f73f3620a5d13f21ef62e2404c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16588 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/i3100: Add space around operatorsElyes HAOUAS
Change-Id: I5ff894f23dc2a2c59bc5e5d1de4287a6b9c9922c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16625 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/i945: Add space around operatorsElyes HAOUAS
Change-Id: I24505af163544a03e3eab72c24f25fcdc4b1b16c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16624 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/e7505: Improve code formattingElyes HAOUAS
Change-Id: I964512c0e913f7443f3dea859b01358645cfd8a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16632 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/i82830: Add space around operatorsElyes HAOUAS
Change-Id: Ic4e287209cc45fae574e7af9d45b8a0e648ef686 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/haswell: Add space around operatorsElyes HAOUAS
Change-Id: I8fa1e39bfd950475e3b55d6debcbfd92615aa379 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16628 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/e7501: Add space around operatorsElyes HAOUAS
Change-Id: I53aa17076135e55665f2f7c6ede217388fc50cca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16633 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/fsp_rangeley: Add space around operatorsElyes HAOUAS
Change-Id: Ia60729db83333c1159862cf604de321e3af8dcb1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16631 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/fsp_sandybridge: Add space around operatorsElyes HAOUAS
Change-Id: I1b5cdfaf39be639a7ef71e66e91284fa186fbb86 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16630 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20northbridge/intel/gm45: Add space around operatorsElyes HAOUAS
Change-Id: I3781c36a3f354bfd54d20488b95d4f2307c3bce2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16629 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-19gm45/gma.c: use correct id string for fake VBTArthur Heymans
The correct id string for gm45 is "$VBT CANTIGA ". This can be found in the gm45 option rom: "strings vbios.bin | grep VBT". Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16551 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-19nb/gm45/gma.c: enable VESA framebuffer mode on VGA outputArthur Heymans
This implements "Keep VESA framebuffer" behavior on VGA output of gm45. This patch reuses Linux code to compute vga divisors. Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16338 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-19gm45/gma.c: use screen on vga connector if connectedArthur Heymans
The intel x4x and gm45 have very similar integrated graphic devices. Currently the x4x native graphic init enables VGA, while gm45 can output on LVDS. This patch reuses the x4x graphic initialisation code to enable output on VGA in gm45 in a way that the behavior is similar to vbios: If no VGA display is connected the internal LVDS screen is used. If an external screen is detected on the VGA port it will be used instead. Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16295 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-15northbridge/intel/nehalem/gma.c: Improve code formattingElyes HAOUAS
Change-Id: Ie7ee547ab34441f93433936334e9881dd7cc0371 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16599 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13i945.h: fix #include pathAntonello Dettori
Fix the #include path. Change-Id: Ifefb2faef6e4fc87152acb21c37dd87e7c14645c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16294 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/intel/nehalem: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/nehalem. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I6da4e0a9ef21b3285f4a369c8ddfbdb32a7a3801 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16406 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13northbridge/intel/gm45: transation away from device_tFurquan Shaikh
Replace the use of the old device_t definition inside northbridge/intel/gm45. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16402 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12src/northbridge: Improve code formattingElyes HAOUAS
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16414 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10northbridge/intel/x4x: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/x4x. Change-Id: I65cd02eacf57cb41ded434582ca6e9d9f655e6ea Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16472 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10northbridge/intel/i5000: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/i5000. Change-Id: Ic049d882ef22f117ee52ba497351f548e2355193 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16471 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-10northbridge/intel/e7505: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/e7505. Change-Id: Ie819f380ec06667e11bcff3e9e993126a86b2c89 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16469 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09northbridge/intel/fsp_rangeley: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/fsp_rangeley. Change-Id: I4c1e6af64fe70211db2fafdba9f39182dfea66fc Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16470 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-09nb/intel/gm45: Fix DMAR table - IOMMU advertisement for ME interfacesDamien Zammit
Previously the ME PCI interface (HECI) was being reported as present in the DMAR ACPI table even when ME firmware was missing or the PCI device was hidden and HECI would be unresponsive. Now we check via the PCI config space itself to verify if the HECI is present or not. Note that this test could fail if ME firmware is present but HECI is disabled in devicetree, because it would not advertise that the HECI exists even though there is a running ME. Perhaps this behaviour is desirable because in this case you won't see the HECI in the lspci tree anyway. Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16330 Tested-by: build bot (Jenkins) Reviewed-by: Swift Geek <swiftgeek@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07nb/intel/x4x: Correct typos in interrupt routing for PEGDamien Zammit
Device 1 on secondary bus instead of device 0 was being routed. Change-Id: I4207938038acf7ff941afd692e90a690d2426a05 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16515 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07nb/intel/x4x: Turn on PEG graphics in device enableDamien Zammit
Change-Id: I389c4630362af1c1bf6d281c9d2b7fc81bea2d5d Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16495 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-07nb/intel/x4x: Increase MMIO PCI space to 2GiBDamien Zammit
This is necessary for PCI express graphics card add-ons, otherwise the pci allocator cannot fit the mmio for the add on card into the space it has available and the OS turns off the card. Old value was 1GiB. Change-Id: I606994501b15e636fe209d1ed4b3d3f73b42bf5c Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16494 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07nb/intel/x4x: Fix DMI initDamien Zammit
No more hang on DMI init when wait for DMI is re-enabled. Previously the virtual channel arbitration table was not being set up in the south/north bridges causing invalid DMI state. This has been tested on GA-G41M-ES2L with patches following. An NVIDIA GT218 card was detected by the OS and displayed using the nouveau driver with no blobs. Change-Id: I35e03c40f5f7aa4915afd5d26db7ab053abcf0cd Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16491 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-07gm45/gma.c: clean up some registersArthur Heymans
According to "G45: Volume 3: Display Register Intel ® 965G Express Chipset Family and Intel ® G35 Express Chipset Graphics Controller" some registries are set incorrectly in gm45/gma.c. Some values are changed after comparing them with the values the i915 linux kernel (3.13 was used) module sets while modesetting. The values were obtained using 'intel_reg' from intel-gpu-tools, during a normal boot and with 'nomodeset' as a kernel argument. Some registers that don't exist on gm45 are set in gma.c, which is probably the result of copying code from a more recent intel northbridge. The result is that that gm45 laptops with wxga displays still work as before. gm45 laptops with wxga+ or higher resolution now just work, where previously a black screen was shown. TEST: build with native graphic init and flash on a gm45 target, like lenovo x200. Change-Id: If66b60c7189997c558270f9e474851fe7e2219f1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16217 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-04northbridge/intel/i945: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/i945. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I041c150a7b50261e26955ad9287ef05b9a06e412 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16371 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-04northbridge/intel/sandybridge: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside northbridge/intel/sandybridge. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I35cc76ec7b6baa216666d06f6f325f43ac69067e Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16409 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31northbridge/intel: Add required space before opening parenthesis '('Elyes HAOUAS
Change-Id: I53208ce5db06d2c65f954e6d59222924ab87722e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16304 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31i945: Enable changing VRAM sizeArthur Heymans
On i945 the vram size is the default 8mb. It is also possible to set it 1mb or 0mb hardcoding the GGC register in early_init.c The intel documentation on i945, "Mobile Intel® 945 Express Chipset Family datasheet june 2008" only documents those three options. They are set using 3 bits. The documententation also makes mention of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it. The other non documented (straight forward) bit combinations allow to change the VRAM size to those other states. What this patch does is: - add those undocumented registers with their respective vram size to the i945 NB code; - make this a cmos option on targets that have this northbridge. TEST: build, flash to target, set cmos as desired and boot linux. On Debian it can be found using "dmesg | grep stolen". NOTE: dmesg message about reserved vram are quite different depending on linux version Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23src/northbridge: Remove unnecessary whitespace before "\n" and "\t"Elyes HAOUAS
Change-Id: I6a533667c7c8ff5ec6ab9d4e1cfc51e993a90084 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16280 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-09x4x: make preallocated IGD memory a cmos optionArthur Heymans
This allows to set the preallocated memory for the IGD on x4x using a cmos option. If no cmos option is found a default value of 64M is used. TESTED most options on ga-g41m-es2l with 2G dimm in one slot and 2x2G. 352M also works in contrast with gm45 where it is known to cause issues with certain ram combinations. Change-Id: I9051d080be82f6dfab37d353252e29b2ed1fca7f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15492 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-09x4x: add non documented vram sizesArthur Heymans
The Intel documtentation, "Intel ® 4 Series Chipset Family" mentions the possibility of 1, 4, 8 and 16M of preallocated memory for the IGD, but does not document this. This allows to set those undocumented values. TESTED on ga-g41m-es2l with 2G dimm in one slot and 2x2G. Change-Id: I92beb8d78907d4514a5aaf69248dd607dcf227c0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15491 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-31src/northbridge: Capitalize CPU, RAM and ROMElyes HAOUAS
Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-27nb/intel/x4x: Fix CAS latency detection and max memory detectionDamien Zammit
Now hardcode maximum memory frequency capability to 800MHz, as all chipsets in x4x family support PC2-6400 according to the datasheet. CAS latency detection also relies on this, and has been cleaned up. Ram initialization does not work with FSB 1333MHz / DDR2 800MHz combination, so disable this combination for now, and reduce to 667MHz instead. Still don't know why this is the case, but FSB1333/667 works. These changes should now allow existing configurations to continue working, while providing support for previously unworking configurations, due to previous buggy CAS latency detection code. TESTED: on GA-G41M-ES2L CPU: E5200 @ 2.50GHz (FSB 800MHz) 2x 1GB 667MHz hynix worked @ 667 1x 2GB 800Mhz ARAM worked @ 800 1x 1GB 667Mhz StarRam worked @ 667 2x 2GB 800Mhz (generic) worked @ 800 Change-Id: I1ddd7827ee6fe3d4162ba0546f738a8f9decdf93 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15818 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-26intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZEKyösti Mälkki
Match the definition and use of these variable with haswell, such that DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE. Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15761 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-19nb/intel/x4x: Fix CAS latency detectionDamien Zammit
Fix and use the failsafe CAS detection logic rather than recalulating the values from raw SPDs. Tested on GA-G41M-ES2L with 2x2GB DDR2-800 DIMMs (which worked before and still work) Change-Id: I6af0f1705d099f7bcbff8c9baa94a68dae689e01 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15726 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2016-07-15intel/x4x: Do not use scratchpad register for ACPI S3Kyösti Mälkki
If S3 support was implemented for this platform later on, use romstage handoff structure instead. Change-Id: I03c1e07a7fcc17c27203d0c4e32e3958f2ba5273 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15716 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15intel/pineview: Do not use scratchpad register for ACPI S3Kyösti Mälkki
If S3 support was implemented for this platform later on, use romstage handoff structure instead. Change-Id: Ib0cf3ad41753baee26354c5ed19294048e7fb533 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15715 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-14nb/intel/pineview/northbridge.c: Remove legacy_hole_size_k declarationJonathan Neuschäfer
Change-Id: I7c3973ff325f11a86728e8660c70839776981aa5 Reported-by: GCC 6.1.0 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-09nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAMDamien Zammit
Previously, any 800MHz DIMMs were being slowed to 667MHz for no reason other than there was a bug in the maximum frequency detection code for the MCH. Change-Id: Id6c6c88c4a40631f6caf52f536a939a43cb3faf1 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15257 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-07intel/sandybridge: read correct leaf for cpu familyRyan Salsamendi
Reading cpuid leaf 0 is incorrect for testing cpu family. Use leaf 1 instead. See Intel SDM 2a Table 3-17. Change-Id: Ib2c95cdd1fb93db06a08ecd7266f6b88700caf83 Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/15346 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-06-26intel/i945: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: I6f0cdc80870fddeaada3191e493bd85fdefee07f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15245 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-23intel/sandybridge: Fix builds with System Agent blobKyösti Mälkki
Broken with commit: 5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS Available sandybridge/systemagent-r6.bin has MMCONF hard-coded at some places and samsung/lumpy fails at boot here: CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 2fc94 System Agent: Starting up... System Agent: Initializing These are the last lines as captured over USB debug. Change-Id: I441847f0e71a5e1be9c8ef6a04a81eb7bdd8a6d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15328 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22Ignore RAMTOP for MTRRsKyösti Mälkki
Without RELOCATABLE_RAMSTAGE have WB cache large enough to cover the greatest ramstage needs, as there is no benefit of trying to accurately match the actual need. Choose this to be bottom 16MiB. With RELOCATABLE_RAMSTAGE write-back cache of low ram is only useful for bottom 1MiB of RAM as a small part of this gets used during SMP initialisation before proper MTRR setup. Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22intel/model_206ax: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: Ib3250677ee926deaa957c83aca7479eb0159358c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15231 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20nb/intel/sandybridge/raminit: Use supported CASPatrick Rudolph
Instead of programming unsupported CAS use the highest supported value. Start at DDR3 maximum of CAS 18T. Increase error message verbosity level. Useful for overclocking. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Allows to run a DDR3-1600 DIMM at 933Mhz. Change-Id: I2e8aadd541f06fa032ad7095c9a2d5e3bb7613f3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15217 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
Calculate the value from current DDR frequency. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15184 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-20nb/intel/sandybridge/raminit: Do code cleanupPatrick Rudolph
Simplify calculation of value. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). Change-Id: I3ecd12c431b46a8d2218f33d7eb3e10de3bcd61d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15181 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devicesPatrick Rudolph
Set max_mem_clock_mhz in devicetree to 933Mhz. Allows to run the memory at up to DDR3-1866. The same frequency was allowed within the first vendor bios, but Lenovo than decided to limit it to DDR3-1333. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). The RAM is now running at DDR3-1600 instead of DDR3-1333. This gives about 4% performance increase in glmark2 using the Intel GPU. Change-Id: If15be497402d84a2778f0434b6381a64eda832d6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15158 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-17intel/model_206ax: Move platform specific definesKyösti Mälkki
Change-Id: I3c517fc55dd333b1a457324f1d69aeb6f70acec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15197 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
This is more of ACPI S3 resume and x86 definition than CBMEM. Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15190 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-12nb/intel/raminit (native): Read PCI mmio size from devicetreePatrick Rudolph
Instead of hardcoding the PCI mmio size read it from devicetree. Set a default value of 2048 MiB and 1024MiB for laptops without discrete graphics. Tested on Sandybridge Lenovo T520. Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12nb/intel: Factor out common MRC codePatrick Rudolph
Remove code duplication and use the common function store_current_mrc_cache instead. No functionality is changed. Tested on Sandybridge Lenovo T520. Change-Id: I4aa5463f1b1d5e1afbe44b4bfc659524d86204db Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15074 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-04nb/intel/x4x: Fix unpopulated valueDamien Zammit
Previously, 0x0 was the value being used for an unpopulated dimm on spd[62], however some DDR2 dimms have 0x0 as a valid value. Now use 0xff which is an unused value even on DDR2/DDR3. Change-Id: I55a91a6c3fe3733a7bb2abc45ca352c955c07c99 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/15058 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04gm45: enable setting all vram sizes from cmosArthur Heymans
Setting the size of the preallocated memory for the igd is done using a cmos parameter, gfx_uma_size. This was limited to a subset of all available sizes, that were already implemented elsewhere in the northbridge code. What this does is change the cmos parameter to 4 bits instead of 3 bits to accomodate all vram sizes. It also adds a sane default of 32mb that already was in place. The northbridge code that reads this cmos parameter is also changed for this new cmos settings. 352M is disabled since it causes issues on systems with 4GB or more ram. TEST: Build, flash target. Clear cmos by corrupting the checksum (nvramtool -c something). Set a desired value in gfx_uma_size using nvramtool. "dmesg | grep stolen" to see what is actually allocated. Change-Id: Ia6479d03f1abe6d0c94bd7264365505e8f8eaeec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14900 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-05-31nb/intel/x4x: Add DMI/EP initDamien Zammit
The values were obtained from vendor bios at runtime. I am not 100% sure of the sequence required to initiate them, but guessed from the gm45 code. There may be some status bytes needed to be polled during the sequence that is missing, but as I don't have bios writer's datasheet it's very hard for me to know. Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/14925 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-31Fix leaking CONFIG_VGA=yKyösti Mälkki
Items under DEVICE_SPECIFIC_OPTIONS got selected without the driver being selected. Change-Id: I1797fa6175620a9291873559a6308eaea85a090e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14823 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-17intel/sch: Merge northbridge and southbridge in src/socStefan Reinauer
Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14599 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2016-05-08intel/pineview: Don't try to store 34 bits in 32Stefan Reinauer
Mask out the bit that doesn't fit in 32bits, so gcc 6.1 is happy Change-Id: I13e2b41742206b8d86b90314b80cc324c00ae637 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14639 Reviewed-by: Damien Zammit <damien@zamaudio.com> Tested-by: build bot (Jenkins)
2016-05-04nb/intel/sandybridge/raminit: support calling dram_freq multiple timesPatrick Rudolph
The PLL will never lock if the requested frequency is already set. As the fallback may request the same frequency again exit early to prevent a hang. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I625b2956346d8c50cca84def6190c076bf99dbec Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14174 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04nb/intel/sandybridge/raminit: add additional fallbacksPatrick Rudolph
Add the following fallbacks: * Try decreasing clock frequency. In case of DDR1600 the next possible value of DDR1333 is being used. * Try decreasing clock frequency. In case of DDR1333 the next possible value of DDR1066 is being used. * Disable failing channel. The system may be able to boot with a single channel enabled. The fallbacks are untested. Change-Id: I3be7034ad25312b3ebf47a54f335a3893f8d7cc1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14173 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-04nb/intel/gm45: Fix native text mode initializationNick High
The LVDS port is configured to accept data from pipe A, but the panel fitter and VGA were attached to pipe B. Changes to VGACNTRL: - select pipe A instead of pipe B. - disable VGA centering to fix jitter. TEST=Build and run on Thinkpad X200 in both text and framebuffer modes. Change-Id: I2356f264580d8b021952c217de3477291d866f98 Signed-off-by: Nick High <nhigh@openmailbox.org> Reviewed-on: https://review.coreboot.org/14524 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-04-29nb/intel/sandybridge/raminit: fix regression "always use mrccache"Patrick Rudolph
Fix regression introduced by: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Don't run channel_test on S3 resume as it overrides memory that might be in use. Fixes MCE events reported by the GNU/Linux kernel that low memory has been modified. Reset on failed s3 resume. Change-Id: Ibadea286619c7906225f86a93aaa0b4caf26cabe Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-10nb/intel/sandybridge/raminit: always use mrccachePatrick Rudolph
Always use MRC cache if possible. Added a CRC16 array to make sure the DIMMs haven't been replaced. In case one of the CRC's doesn't match, start normal RAM training. Use new fallback in case of broken mrc cache. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Test result: The system boots a lot faster using the MRC cache. On swapping DIMMs the CRC16 doesn't match and normal ram training is started. Change-Id: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14172 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-05nb/intel/sandybridge/raminit: die in toplevel functionPatrick Rudolph
In error case die in top level function. No functionality is changed. Change-Id: Ie15b01184d40bdbce20d49dcab2f9fb607068c7a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14171 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-05nb/intel/sandybridge/raminit: prepare raminit for fallbackPatrick Rudolph
Return errors to top level ram init function. Required by the folowing series to implement a fallback. No functionality is changed. On error case the system still halts in every test. Change-Id: I6278c4a1d7b4a96be8988a60671fc3d72cd6cb3d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14170 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-30nb/intel/sandybridge/raminit: move ram training into seperate functionPatrick Rudolph
In order to add a fallback mechanism, move the ram training code into a new function. This function will be called multiple times and must return error or success to the calling function. Change-Id: I5ee1b3a528290d8252d236b9152b81291736958a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14169 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-29nb/intel/sandybridge/raminit: move dimm_info into ramctr_timingPatrick Rudolph
It's required to store the dimm_info in ramctr_timing as only ramctr_timing is written to mrc cache. Allows to fill SMBIOS type 17 if mrc cache is used. Change-Id: I7634b05069df307d471938d9854997a018de81b3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14168 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-16cpu/x86/mtrr: move cache_ramstage() to its only userAaron Durbin
The Intel i3100 northbridge code is the only user of cache_ramstage(). Therefore, place it next to the sole consumer. Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14097 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-03-13northbridge/intel/i3100: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i3100 boards in the chipset. Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13786 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-13northbridge/intel/i82810: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i810 boards in the chipset. Change-Id: Ifda7dcfdf37b6affce838ee96ca6382b2d4be8c3 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13784 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-12northbridge/intel/i82830: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i830 boards in the chipset. Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
The sourcecode is 99% the same. Only two lines differ, but not in functionality. Also rename mrccache.c -> mrc_cache.c Tested-on: boot + suspend/resume on x220 Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/14007 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11northbridge/intel: move mrc_cache definition into a common headerAlexander Couzens
The mrc_cache definition and the struct mrc_container are the same over all intel platforms. Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/13998 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11nortbridge/sandybridge/mrccache: parse the return code of flash->writeAlexander Couzens
Change-Id: I2738da99e4651598faeaa228fba447d0872e9ded Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/13999 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11northbridge/i945/gma: Re-enable NVRAM tft_brightnessAlexander Couzens
Commit 71512b2c (northbridge/i945/gma: fix build error with native graphics init) unintentionally changed the code to ignore the NVRAM setting `tft_brightness`. Revert that hunk to restore the original behavior. Change-Id: Iffdfc5272732bad3476f35ddac1f5a7564270531 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/14002 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-10northbridge/intel/i440bx: Unify UDELAY selectionStefan Reinauer
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i440BX boards in the chipset. Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13781 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-09northbridge/intel/gm45: Use TSC for ramstage timer per defaultStefan Reinauer
This is a step towards isolating the timer drivers. Change-Id: I4c9349054be0cf520cd4407be9fb393b664223a4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13922 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-05sandybridge/gma_lvds: support both Sandy&Ivy on one boardIru Cai
Sandy and Ivy Bridge processors use the same socket, and a mainboard with the socket can support both types of CPUs. However, they use different native graphics init code for LVDS and cause a crash if running the wrong code. This change detects the CPU type and then selects the right code to run. It will add some more code in ramstage. It also merges the {SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS. Tested on a Lenovo T520 with i7-2630qm and i7-3720qm Signed-off-by: Iru Cai <mytbk920423@gmail.com> Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91 Reviewed-on: https://review.coreboot.org/12087 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
2016-03-03nb/intel/sandybridge/raminit: Fill SMBIOS type17 infoPatrick Rudolph
Fill minimal info required for SMBIOS type 17. Report * DIMM size * channel * rank per DIMM * speed in Mhz * DIMM type * slot * manufacturer ID * serial Allows dmidecode to print the current RAM configuration. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Linux 4.3 * dmidecode 3.0 dmidecode output: Handle 0x0005, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 16 bits Data Width: 8 bits Size: 8192 MB Form Factor: DIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Unknown (cd04) Serial Number: None Asset Tag: Not Specified Part Number: F3-1866C9-8GSR Rank: 2 Configured Clock Speed: 1600 MHz Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Handle 0x0006, DMI type 17, 40 bytes Memory Device Array Handle: 0x0000 Error Information Handle: Not Provided Total Width: 16 bits Data Width: 8 bits Size: 8192 MB Form Factor: DIMM Set: None Locator: Channel-1-DIMM-1 Bank Locator: BANK 0 Type: DDR3 Type Detail: Synchronous Speed: 1600 MHz Manufacturer: Unknown (cd04) Serial Number: None Asset Tag: Not Specified Part Number: F3-1866C9-8GSR Rank: 2 Configured Clock Speed: 1600 MHz Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Change-Id: I4e5f772d68484b9cb178ca8a1d63ad99839f3993 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13852 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph
Instead of hardcoding the maximum supported DDR frequency to 800Mhz (DDR3-1600), read the fuse bits that encode this information. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-02nb/intel/sandybridge/raminit: Make discover_timC_write non cyclicPatrick Rudolph
The code can't handle cyclic zero runs. Make sure it will never wrap around by setting the top-most bit to constant one. Fixes "Mini channel test failed (2)". Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I55e610d984d564bd4675f9318dead6d6c1e288a3 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13853 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-28northbridge/intel: add missing #include guardsIru Cai
I first found the missing of #include guards when I tried to include both sandybridge/gma.h and sandybridge/sandybridge.h, but sandybridge.h includes gma.h in it and gives a compile error. Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/13775 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-02-26nb/intel/sandybridge/raminit: Adjust timB to prevent overflowPatrick Rudolph
Improved version of I1a115a45d5febf351d89721ece79eaf43f7ee8a0 The first version wasn't well tested due to the lack of hardware and it was to aggressive. With timC being direct function of timB's 6 LSBs it's critical to match timC and timB. Some tests increments the value of timB by a small value, which might cause the 6bit value to overflow, if it's close to 0x3F. Increment the value by a small offset if it's likely to overflow, to make sure it won't overflow while running tests and bricks the system due to a non matching timC. In comparission to the first attempt, only 4 out of 128 timB values are considered bad. Needs test on real hardware ! Fixes a "edge write discovery failed" on my test system. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: If9abfc5f92e20a8f39c6f50cc709ca1cedf6827d Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-26tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"Denis 'GNUtoo' Carikli
Change-Id: Ib73abb0ada7dfdfab3487c005719e19f51ef1812 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> Reviewed-on: https://review.coreboot.org/13779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-20nb/intel/sandybridge/raminit: Add XMP supportPatrick Rudolph
Some vendors store lower frequency profiles in the regular SPD, if the SPD contains a XMP profile. To make use of the board's and DIMM's maximum supported DRAM frequency, try to parse the XMP profile and use it instead. Validate the XMP profile to make sure that the installed DIMM count per channel is supported and the requested voltage is supported. To reduce complexity only XMP Profile 1 is read. Allows my DRAM to run at 800Mhz instead of 666Mhz as encoded in the default SPD. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: Ib4dd68debfdcfdce138e813ad5b0e8e2ce3a40b2 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13486 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-19nb/intel/sandybridge/raminit: Improve loggingPatrick Rudolph
Use printram() in more places and use printk() only where it makes sense. Remove spamming "MRd: %x <= %x\n". Use common syntax for timing output. Change-Id: I38965967a029994112d7ab63afd4d9968a7728c5 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13414 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18nb/intel/sandybridge: Start PEG link trainingPatrick Rudolph
Issue observed: The PCIe Root port shows up in GNU/Linux but no PCIe device is being detected. Test system: * Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130) * Lenovo T530 (Intel Core i5-3320M CPU) Problem description: The PEG Root port link training on Ivy Bridge needs to be manually started. Problem solution: The bits are set in early_init to meet PCIe reset timeout of 100msec. The bits should be set in PCI device enable function, but this causes the PCI enumeration to not detect the card, as it's still booting. Adding a fixed delay of 100msec resolves this problem, but this would increase boot time. Read the PCI base revision mask to make sure it's any IvyBridge CPU. Don't run the code on MRC path as it has its own PEG initilization code. Tested with: * Nvidia NVS 5400M (PCIe2) * ATI Radeon HD4780 (PCIe2) * Nvidia GeForce 8600 GT (PCIe1) Untested: * PCIe3 devices Final test results: The PEG device shows up under GNU/Linux and can be used without issues. Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/11917 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-18southbridge/intel/bd82x6x: Use common gpio.cPatrick Rudolph
Use shared gpio code from common folder. Bd82x6x's gpio.c and gpio.h is used by other southbridges as well and will be removed once it is unused. Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13614 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-16nb/intel/sandybridge/raminit: Add shift offsetPatrick Rudolph
It looks like the falling timing was missing the shift offset. Not sure if this was intentional, I guess not. Tested on my hardware and produced no regressions. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Please test on real hardware ! Change-Id: Id8c60217093a48bf322f406ea258c10a02c936e8 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13682 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-13sandybridge: Always include MRC if not using native RAM init.Vladimir Serbinenko
Otherwise the image is simply unusable. Change-Id: I1e2562ba17279d14dc73b05e4f8fa493e06fbcd2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13699 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
Tested by making lenovo x230 configurable despite pretty MRC bugs. Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13658 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-12Merge sandy/ivybridge romstage flow for MRC and non-MRC.Vladimir Serbinenko
Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13656 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-10Kconfig: Move defaults for CBFS_SIZEMartin Roth
We want the question for CBFS size to be next to the rom size in the mainboard directory, but that doesn't seem to work for how people want to set the defaults. Instead of having the list of exceptions to the size, just set the defaults at the end of kconfig. - Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into the chipset Kconfigs (gm45, nehalem, sandybridge, x4x) - Override the default for HAVE_INTEL_FIRMWARE on skylake. - Move the HAVE_INTEL_FIRMWARE default setting into the firmware Kconfig file - Move the location of the default CBFS_SIZE=ROM_SIZE to the end of the top level kconfig file, while leaving the question where it is. Test=rebuild Kconfig files before and after the change, verify that they are how they were intended to be. Note: the Skylake boards actually changed value, because they were picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the 0x200000 desired. This was due to the SOC_INTEL_SKYLAKE being after the HAVE_INTEL_FIRMWARE default. Affected boards were: Google chell, glados, & lars and Intel kunimitsu. Change-Id: I2963a7a7eab037955558d401f5573533674a664f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-09sandybridge: Set all native gfx-related options in northbridge code.Vladimir Serbinenko
In the same time remove few native gfx options which were improperly set and only added dead code to the binary. Change-Id: I4ed3fec03a1655ae0a779c3aa3845de273cb12e1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13649 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
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