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path: root/src/northbridge/intel
AgeCommit message (Expand)Author
2021-02-01nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
2021-02-01nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
2021-02-01nb/intel/x4x/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
2021-02-01nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
2021-02-01nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
2021-02-01nb/intel/sandybridge/bootblock.c: include <arch/pci_io_cfg.h>Elyes HAOUAS
2021-02-01nb/intel/i945: Drop casts from DEFAULT_{MCH,DMI}BARAngel Pons
2021-02-01nb/intel/haswell: Calculate TSEG limit from registersAngel Pons
2021-02-01nb/intel/haswell: Create RMRR for iGPUAngel Pons
2021-01-30nb/intel/i945: Define and use MMCONF_BUS_NUMBERAngel Pons
2021-01-30nb/intel/gm45: Define and use MMCONF_BUS_NUMBERAngel Pons
2021-01-30nb/intel/x4x: Define and use MMCONF_BUS_NUMBERAngel Pons
2021-01-30nb/intel/pineview: Define and use MMCONF_BUS_NUMBERAngel Pons
2021-01-30nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhereAngel Pons
2021-01-30nb/intel/sandybridge: Define and use MMCONF_BUS_NUMBERAngel Pons
2021-01-30nb/intel/haswell: Define and use MMCONF_BUS_NUMBERAngel Pons
2021-01-30nb/intel/ironlake: Use RCBA macrosAngel Pons
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
2021-01-27nb/intel/haswell/haswell.h: Do not include `pch.h`Angel Pons
2021-01-25nb/intel/ironlake: Drop constant parameterAngel Pons
2021-01-25nb/intel/sandybridge: Only run DMI recipe on Ivy BridgeAngel Pons
2021-01-25nb/intel/sandybridge: Correct late DMI init sequenceAngel Pons
2021-01-24cpu/intel/haswell: Set C9/C10 vccminAngel Pons
2021-01-21cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZEElyes HAOUAS
2021-01-19nb/intel/pineview/northbridge.c: Fix overlapping resourcesArthur Heymans
2021-01-19nb/intel/pineview/northbridge.c: Improve readabilityArthur Heymans
2021-01-19nb/intel/i945/northbridge.c: Reserve upper part of lower memoryArthur Heymans
2021-01-19nb/intel/i945/northbridge.c: Improve readabilityArthur Heymans
2021-01-19nb/intel/ironlake/northbridge.c: Fix overlapping resourcesArthur Heymans
2021-01-19nb/intel/ironlake/northbridge.c: Improve readabilityArthur Heymans
2021-01-19nb/intel/ironlake/ironlake.asl: Remove sandy bridge copy pastaArthur Heymans
2021-01-19nb/intel/ironlake: Remove chromeos copy pastaArthur Heymans
2021-01-19nb/intel/ironlake: Print MCH dev/revision IDs and CAPIDAngel Pons
2021-01-18nb/intel/gm45: Reserve MMIO and firmware memory below 1MiBNico Huber
2021-01-18Revert "nb/intel/gm45/gm45.h: Remove duplicated include"Patrick Georgi
2021-01-18northbridge/intel/x4x/dq_dqs.c: Remove repeated wordElyes HAOUAS
2021-01-18northbridge/intel/gm45/bootblock.c: Remove repeated wordElyes HAOUAS
2021-01-18northbridge/intel/x4x/raminit_ddr23.c: Remove repeated wordElyes HAOUAS
2021-01-18northbridge/intel/sandybridge/bootblock.c: Remove repeated wordElyes HAOUAS
2021-01-18nb/intel/gm45/gm45.h: Remove duplicated includeElyes HAOUAS
2021-01-18lib/ramtest: Fix ram_check() declarationsKyösti Mälkki
2021-01-15nb/intel/sandybridge: Clarify command timing calculationAngel Pons
2021-01-15nb/intel/sandybridge: Fix handling of clock timingAngel Pons
2021-01-15nb/intel/sandybridge: Remove wrong and nonsense conditionAngel Pons
2021-01-15nb/intel/x4x: Clean up raminit commentsAngel Pons
2021-01-15nb/intel/x4x: Reset DQS probe on all channelsAngel Pons
2021-01-15nb/intel/pineview: Extract HPET setup and delay functionAngel Pons
2021-01-10nb/intel/gm45: Guard macro parametersAngel Pons
2021-01-10nb/intel/gm45: Guard `CxDRBy_BOUND_SHIFT` macro parametersAngel Pons
2021-01-10cpu/intel/haswell/haswell.h: Align with BroadwellAngel Pons
2021-01-06nb/intel/sandybridge: Use consistent comment styleAngel Pons
2021-01-06nb/intel/sandybridge: Define and use `QCLK_PI` constantAngel Pons
2021-01-05nb/intel/haswell/memmap.h: Clean upAngel Pons
2021-01-04nb/intel/sandybridge: Replace memset with initializerAngel Pons
2021-01-01nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settingsMichael Niewöhner
2021-01-01soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representationMichael Niewöhner
2020-12-30drivers/intel/gma: Include gfx.asl by default for all platforms...Matt DeVillier
2020-12-29soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delayMichael Niewöhner
2020-12-25cpu/intel/model_206ax: Add more CPU steppingsAngel Pons
2020-12-25nb/intel/sandybridge: Move steppings to CPU headerAngel Pons
2020-12-25nb/intel/sandybridge: Rewrite constant valuesAngel Pons
2020-12-25nb/intel/sandybridge: Allow to ignore XMP voltageAngel Pons
2020-12-23nb/intel/sandybridge: Refactor ODT stretch table codeAngel Pons
2020-12-23nb/intel/sandybridge: Refactor `dram_find_spds_ddr3`Angel Pons
2020-12-23nb/intel/sandybridge: Always wait for IOSAV after starting itAngel Pons
2020-12-23nb/intel/sandybridge: Introduce `iosav_run_once_and_wait`Angel Pons
2020-12-23nb/intel/sandybridge: Remove unnecessary commentsAngel Pons
2020-12-23nb/intel/sandybridge: Print delays in decimalAngel Pons
2020-12-23nb/intel/sandybridge: Add comment to TC_RWP writeAngel Pons
2020-12-23nb/intel/sandybridge: Use proper names to refer to training stepsAngel Pons
2020-12-23nb/intel/sandybridge: Add comments about I/O and RT latencyAngel Pons
2020-12-23nb/intel/sandybridge: Rename I/O data timingsAngel Pons
2020-12-23nb/intel/sandybridge: Use bitfields for I/O data timingsAngel Pons
2020-12-23nb/intel/sandybridge: Compute data timings independentlyAngel Pons
2020-12-17drivers: Replace set_vbe_mode_info_validPatrick Rudolph
2020-12-14nb/intel/ironlake: Add comment about MCH scan chainsAngel Pons
2020-12-14nb/intel/ironlake: Remove unused constantAngel Pons
2020-12-13nb/intel/sandybridge: Clean up program_timingsAngel Pons
2020-12-12nb/intel/sandybridge: Clean up stepping logicAngel Pons
2020-12-12nb/intel/sandybridge: Fix blunder in MR2 shadow codeAngel Pons
2020-12-07nb/intel/ironlake: Introduce memmap.hAngel Pons
2020-12-07nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
2020-12-07nb/intel/i945: Introduce memmap.hPatrick Georgi
2020-12-03cbfs: Introduce cbfs_ro_map() and cbfs_ro_load()Julius Werner
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
2020-12-02cbfs: Enable CBFS mcache on most chipsetsJulius Werner
2020-11-22nb/intel/sandybridge: Clean up COMPOFST1 logicAngel Pons
2020-11-22nb/intel/sandybridge: Correct get_COMP2 functionAngel Pons
2020-11-22nb/intel/sandybridge: Rename and refactor `discover_timC_write`Angel Pons
2020-11-22nb/intel/sandybridge: Only use write Vref if supportedAngel Pons
2020-11-22nb/intel/sandybridge: Refine power-down mode logicAngel Pons
2020-11-22nb/intel/sandybridge: Lower tPRPDEN to 1Angel Pons
2020-11-22nb/intel/sandybridge: Increase tRWDRDD with fast RAMAngel Pons
2020-11-22nb/intel/sandybridge: Rename and clean up `discover_edges_write`Angel Pons
2020-11-22nb/intel/sandybridge: Relocate PREA-ACT-RD sequenceAngel Pons
2020-11-22nb/intel/sandybridge: Remove spurious writes to IOSAV BW maskAngel Pons
2020-11-22nb/intel/sandybridge: Drop `precharge` functionAngel Pons
2020-11-22nb/intel/sandybridge: Clarify register writeAngel Pons
2020-11-22nb/intel/sandybridge: Encapsulate JEDEC write levelingAngel Pons
2020-11-22nb/intel/sandybridge: Do not rewrite write leveling sequenceAngel Pons
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