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path: root/src/northbridge/intel/x4x
AgeCommit message (Expand)Author
2018-11-19src: Add required space after "switch"Elyes HAOUAS
2018-11-16src: Remove unneeded include <cbmem.h>Elyes HAOUAS
2018-11-16src: Remove unneeded include <lib.h>Elyes HAOUAS
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-11-05nb/intel/x4x/raminit: Add missing spaceJonathan Neuschäfer
2018-10-24nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardwareArthur Heymans
2018-10-24nb/intel/*: Account for cbmem_top alignmentArthur Heymans
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
2018-10-15nb/intel/x4x: Fix P45 CAPID max frequencyArthur Heymans
2018-10-15nb/intel/x4x: Program read training results to all ranksArthur Heymans
2018-10-08src: Use tabs for indentationElyes HAOUAS
2018-09-16nb/intel/x4x: Don't use cached settings if CPU FSB has been changedArthur Heymans
2018-09-05nb/intel/x4x/gma.c: fix skipping of native graphics initStefan Tauner
2018-08-22nb/intel/*/gma.c: Skip NGI when VGA decode is not enabledArthur Heymans
2018-08-10src: Fix typoElyes HAOUAS
2018-08-09src/northbridge: Fix typoElyes HAOUAS
2018-08-04x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
2018-08-01nb/intel/x4x: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-07-30x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
2018-07-30northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held
2018-06-29sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans
2018-06-17nb/intel/x4x: Issue a hard reset with empty MRC cache on warm resetArthur Heymans
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
2018-06-14nb/intel/x4x: Work around a quirkArthur Heymans
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
2018-06-05nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans
2018-06-04nb/intel: Use postcar_frame_add_romcache()Nico Huber
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
2018-05-14nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
2018-05-14nb/x4x/raminit: Decode ddr3 dimmsArthur Heymans
2018-05-14nb/intel/x4x/raminit: Fix programming dual channel registersArthur Heymans
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
2018-05-01nb/intel/x4x: Change memory layout to improve MTRRArthur Heymans
2018-05-01nb/intel/x4x: Fix programming CxDRBArthur Heymans
2018-05-01nb/intel/x4x: Implement both read and write trainingArthur Heymans
2018-04-30nb/x4x: Get rid of device_tElyes HAOUAS
2018-04-28nb/intel/x4x: Fix computing page_sizeArthur Heymans
2018-04-17nb/intel/x4x/rcven.c: Change the verbosity of some messagesArthur Heymans
2018-04-17nb/intel/x4x: Add a convenient macro to loop over bytelanesArthur Heymans
2018-04-17nb/intel/x4x: Clarify the raminit memory mappingArthur Heymans
2018-04-17nb/intel/x4x: Refactor setting default dll settingsArthur Heymans
2018-04-17nb/intel/x4x: Use SPI flash to cache raminit resultsArthur Heymans
2018-02-22device/ddr2,ddr3: Rename and move a few thingsArthur Heymans
2018-02-20nb/x4x/raminit_ddr2: Refactor clock configuration slightlyJonathan Neuschäfer
2018-01-05nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeoutArthur Heymans
2017-12-16nb/x4x/raminit: Rewrite SPD decode and timing selectionArthur Heymans
2017-12-12nb/intel/x4x/rcven.c: Fix programming coarse offsetArthur Heymans
2017-10-13nb/intel/*/gma: Port ACPI opregion to older platformsPatrick Rudolph
2017-09-22nb/intel/x4x: Select LAPIC_MONOTONIC_TIMERArthur Heymans
2017-08-20nb/intel/x4x: Fix booting with FSB800 DDR667 combinationArthur Heymans
2017-08-20nb/intel/x4x/raminit: Rework receive enable calibrationArthur Heymans
2017-08-11nb/intel/x4x/gma.c: Probe VGA EDID on DVI-I portsArthur Heymans
2017-08-07nb/intel/*/gma.c: Use macros for GMBUS numbersArthur Heymans
2017-07-21nb/intel/x4x: Rework programming DQ and DQS DLL timingsArthur Heymans
2017-07-21sb/intel/i82801jx: Add correct PCI ids and change namesArthur Heymans
2017-06-04Kconfig: Add choice of framebuffer modeNico Huber
2017-06-02Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber
2017-06-02Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFGNico Huber
2017-05-24nb/intel/x4x/raminit: Initialise async variableArthur Heymans
2017-05-22nb/intel/x4x: Use a struct for dll settings instead of an arrayArthur Heymans
2017-05-21nb/intel/x4x: Make raminit less verbose with CONFIG_DEBUG_RAM_SETUPArthur Heymans
2017-05-20nb/intel/x4x/raminit: Remove very long delayArthur Heymans
2017-05-13nb/intel/x4x: Fix uninitialized variable issueNico Huber
2017-05-11nb/intel/x4x: Define and use default MMCONF_BASE_ADDRESSArthur Heymans
2017-05-10nb/intel/x4x: Add support for second PEG slotArthur Heymans
2017-05-09nb/x4x: Do not enable IGD when not supportedArthur Heymans
2017-05-09nb/intel/x4x: Don't run NGI if IGD has not been assigned VGA cyclesArthur Heymans
2017-05-09nb/x4x: Add ramstage IGD disable functionArthur Heymans
2017-05-09nb/x4x/nortbridge.c: Compute TSEG resource allocation dynamicallyArthur Heymans
2017-05-08nb/x4x/raminit.c: Remove ME locking codeArthur Heymans
2017-05-04nb/intel/x4x/raminit: Change reset type on incomplete raminit resetArthur Heymans
2017-04-15nb/intel/x4x/Kconfig: Don't fix CBFS_SIZE on i82801gx southbridgeArthur Heymans
2017-03-21nb/x4x: Move checkreset before SPD readingArthur Heymans
2017-03-21nb/intel/x4x: Fix issues found by checkpatch.plArthur Heymans
2017-02-17nb/intel/x4x: Implement resume from S3 suspendArthur Heymans
2017-02-17nb/intel/x4x: Fix raminit on reset pathArthur Heymans
2017-01-22nb/x4x/raminit: Fix programming dram timingsArthur Heymans
2017-01-06nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>Arthur Heymans
2016-12-17nb/x4x: Add other Eaglelake IGD PCI DID to listArthur Heymans
2016-12-11intel i945 gm45 x4x: Switch to RELOCATABLE_RAMSTAGEKyösti Mälkki
2016-12-11intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setupKyösti Mälkki
2016-12-11intel i945 gm45 x4x: Apply cbmem_top() alignmentKyösti Mälkki
2016-12-08buildsystem: Drop explicit (k)config.h includesKyösti Mälkki
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
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