Age | Commit message (Expand) | Author |
2019-07-17 | nb/intel/x4x: Die on invalid memory speeds | Jacob Garber |
2019-07-09 | cpu/x86: Flip SMM_TSEG default | Kyösti Mälkki |
2019-07-04 | arch/x86: Adjust size of postcar stack | Kyösti Mälkki |
2019-06-21 | nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps} | Elyes HAOUAS |
2019-06-05 | nb/intel/x4x: Remove variable set but not used | Elyes HAOUAS |
2019-06-04 | nb/intel/x4x/rcven.c: Remove variable set but not used | Elyes HAOUAS |
2019-05-29 | src/northbridge: Add missing 'include <types.h>' | Elyes HAOUAS |
2019-05-24 | nb/northbridge/intel/x4x/acpi.c: Remove variable set but not used | Elyes HAOUAS |
2019-05-23 | nb/intel/x4x/early_init.c: Remove variable set but not used | Elyes HAOUAS |
2019-05-15 | src/northbridge: Remove unneeded include <arch/io.h> | Elyes HAOUAS |
2019-05-07 | {gm45,pineview,sandybridge,x4x}: Use {full,system}_reset() function | Elyes HAOUAS |
2019-04-29 | nb/x4x: Use system_reset() and full_reset() | Elyes HAOUAS |
2019-04-25 | src/northbridge/intel: Remove unused variables | Elyes HAOUAS |
2019-04-11 | nb/intel/{gm45,i945,x4x}: Correct array bounds checks | Jacob Garber |
2019-04-06 | src: Use include <delay.h> when appropriate | Elyes HAOUAS |
2019-03-27 | Move calls to quick_ram_check() before CBMEM init | Kyösti Mälkki |
2019-03-21 | {northbridge, soc, southbridge}/intel: Make use of pci_dev_set_subsystem() | Subrata Banik |
2019-03-20 | src: Use 'include <string.h>' when appropriate | Elyes HAOUAS |
2019-03-16 | src: Drop unused '#include <halt.h>' | Elyes HAOUAS |
2019-03-13 | nb/intel/stage_cache.c: Drop unnecessary includes | Elyes HAOUAS |
2019-03-08 | coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) | Julius Werner |
2019-03-06 | Remove DEFAULT_PCIEXBAR alias | Kyösti Mälkki |
2019-03-04 | device/mmio.h: Add include file for MMIO ops | Kyösti Mälkki |
2019-03-04 | arch/io.h: Drop unnecessary include | Kyösti Mälkki |
2019-03-01 | device/pci: Fix PCI accessor headers | Kyösti Mälkki |
2019-02-01 | sb/intel/common: Rename i2c_block_read() to i2c_eeprom_read() | Kyösti Mälkki |
2019-01-24 | nb/intel/x4x: Put stage cache in TSEG | Arthur Heymans |
2019-01-23 | nb/intel/x4x: Use parallel MP init | Arthur Heymans |
2019-01-13 | nb/intel/x4x: Remove spurious pcidev_on_root() usage | Nico Huber |
2019-01-10 | mb: Move timestamp_add_now to northbridge x4x | Elyes HAOUAS |
2019-01-06 | device: Use pcidev_on_root() | Kyösti Mälkki |
2019-01-04 | device: Replace ugly cases of dev_find_slot() | Kyösti Mälkki |
2018-12-19 | northbridge: Remove useless include <device/pci_ids.h> | Elyes HAOUAS |
2018-12-18 | northbridge: Remove unneeded include <pc80/mc146818rtc.h> | Elyes HAOUAS |
2018-12-03 | nb/intel/x4x: Use common code for SMM in TSEG | Arthur Heymans |
2018-11-19 | src: Add required space after "switch" | Elyes HAOUAS |
2018-11-16 | src: Remove unneeded include <cbmem.h> | Elyes HAOUAS |
2018-11-16 | src: Remove unneeded include <lib.h> | Elyes HAOUAS |
2018-11-16 | src: Get rid of duplicated includes | Elyes HAOUAS |
2018-11-12 | src: Remove unneeded include "{arch,cpu}/cpu.h" | Elyes HAOUAS |
2018-11-05 | nb/intel/x4x/raminit: Add missing space | Jonathan Neuschäfer |
2018-10-24 | nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware | Arthur Heymans |
2018-10-24 | nb/intel/*: Account for cbmem_top alignment | Arthur Heymans |
2018-10-23 | src: Remove unneeded whitespace | Elyes HAOUAS |
2018-10-15 | nb/intel/x4x: Fix P45 CAPID max frequency | Arthur Heymans |
2018-10-15 | nb/intel/x4x: Program read training results to all ranks | Arthur Heymans |
2018-10-08 | src: Use tabs for indentation | Elyes HAOUAS |
2018-09-16 | nb/intel/x4x: Don't use cached settings if CPU FSB has been changed | Arthur Heymans |
2018-09-05 | nb/intel/x4x/gma.c: fix skipping of native graphics init | Stefan Tauner |
2018-08-22 | nb/intel/*/gma.c: Skip NGI when VGA decode is not enabled | Arthur Heymans |
2018-08-10 | src: Fix typo | Elyes HAOUAS |
2018-08-09 | src/northbridge: Fix typo | Elyes HAOUAS |
2018-08-04 | x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2] | Felix Held |
2018-08-01 | nb/intel/x4x: Don't use PCI operations on the pci_domain device | Arthur Heymans |
2018-07-30 | x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2] | Felix Held |
2018-07-30 | northbridge/x4x: add MCHBAR AND/OR/AND_OR access macros | Felix Held |
2018-06-29 | sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables | Arthur Heymans |
2018-06-17 | nb/intel/x4x: Issue a hard reset with empty MRC cache on warm reset | Arthur Heymans |
2018-06-14 | nb/intel/x4x: Deprecate native graphic init | Arthur Heymans |
2018-06-14 | nb/intel/x4x: Fix a few things in set_enhanced_mode | Arthur Heymans |
2018-06-14 | nb/intel/x4x: Work around a quirk | Arthur Heymans |
2018-06-14 | nb/intel/x4x: Add the option for stacked channel map settings | Arthur Heymans |
2018-06-08 | libgfxinit: Enable G45 support (for GM45/X4X) | Nico Huber |
2018-06-06 | arch/x86: Make RELOCATABLE_RAMSTAGE the default | Kyösti Mälkki |
2018-06-05 | nb/intel/x4x: Switch to POSTCAR_STAGE | Arthur Heymans |
2018-06-04 | nb/intel: Use postcar_frame_add_romcache() | Nico Huber |
2018-06-04 | northbridge/intel: Remove unneeded includes | Elyes HAOUAS |
2018-05-31 | {cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate | Nico Huber |
2018-05-24 | nb/intel/x4x: Adapt post JEDEC for DDR3 | Arthur Heymans |
2018-05-24 | nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings | Arthur Heymans |
2018-05-24 | nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings | Arthur Heymans |
2018-05-24 | nb/intel/x4x: Implement write leveling | Arthur Heymans |
2018-05-24 | nb/intel/x4x: Add DDR3 JEDEC init | Arthur Heymans |
2018-05-14 | nb/intel/x4x/raminit: DDR3 specific ODT | Arthur Heymans |
2018-05-14 | nb/intel/x4x: Add DDR3 rcomp | Arthur Heymans |
2018-05-14 | nb/intel/x4x/raminit: Support programming initials DD3 DLL setting | Arthur Heymans |
2018-05-14 | nb/intel/x4x/raminit: Support programming DDR3 timings | Arthur Heymans |
2018-05-14 | nb/intel/x4x/raminit: Make programming launch ddr3 specific | Arthur Heymans |
2018-05-14 | nb/intel/x4x/raminit: Make programming crossclock support DDR3 | Arthur Heymans |
2018-05-14 | nb/intel/x4x: Rename a things that are not specific to DDR2 | Arthur Heymans |
2018-05-14 | nb/x4x/raminit: Decode ddr3 dimms | Arthur Heymans |
2018-05-14 | nb/intel/x4x/raminit: Fix programming dual channel registers | Arthur Heymans |
2018-05-08 | {mb,nb,soc}: Remove references to pci_bus_default_ops() | Nico Huber |
2018-05-01 | nb/intel/x4x: Change memory layout to improve MTRR | Arthur Heymans |
2018-05-01 | nb/intel/x4x: Fix programming CxDRB | Arthur Heymans |
2018-05-01 | nb/intel/x4x: Implement both read and write training | Arthur Heymans |
2018-04-30 | nb/x4x: Get rid of device_t | Elyes HAOUAS |
2018-04-28 | nb/intel/x4x: Fix computing page_size | Arthur Heymans |
2018-04-17 | nb/intel/x4x/rcven.c: Change the verbosity of some messages | Arthur Heymans |
2018-04-17 | nb/intel/x4x: Add a convenient macro to loop over bytelanes | Arthur Heymans |
2018-04-17 | nb/intel/x4x: Clarify the raminit memory mapping | Arthur Heymans |
2018-04-17 | nb/intel/x4x: Refactor setting default dll settings | Arthur Heymans |
2018-04-17 | nb/intel/x4x: Use SPI flash to cache raminit results | Arthur Heymans |
2018-02-22 | device/ddr2,ddr3: Rename and move a few things | Arthur Heymans |
2018-02-20 | nb/x4x/raminit_ddr2: Refactor clock configuration slightly | Jonathan Neuschäfer |
2018-01-05 | nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout | Arthur Heymans |
2017-12-16 | nb/x4x/raminit: Rewrite SPD decode and timing selection | Arthur Heymans |
2017-12-12 | nb/intel/x4x/rcven.c: Fix programming coarse offset | Arthur Heymans |
2017-10-13 | nb/intel/*/gma: Port ACPI opregion to older platforms | Patrick Rudolph |
2017-09-22 | nb/intel/x4x: Select LAPIC_MONOTONIC_TIMER | Arthur Heymans |