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Displaying the whole receive enable procedure is very verbose should
only be done if CONFIG_DEBUG_RAM_SETUP is selected.
Change-Id: Ib568621e6d044624c1c0aeb6fb08945f561395c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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During raminit a lot of procedures need to be done for each bytelane.
Change-Id: Ib9a30ffabaf5c845e962e3e79cf4a20faa1d9857
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This replaces magic values by macros and adds some comments to improve
readability.
Adds a convenient function to fetch the test address of a rank.
Also fixes the temporary memory map by changing a write to MCHBAR
0x100 to 0x110, since this is what vendor does. (No difference
observed thus far)
TESTED on DG43GT
Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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Stores information obtained from decoding dimms and receive enable
results for future use.
Depreciates using rtc nvram to store receive enable settings.
A notable change is that receive enable results are always reused, not
just on a resume from S3.
This requires cbmem to be initialized a bit earlier, right after the
raminit finished to be able to add the sysinfo struct to cbmem which
gets cached to the SPI flash in ramstage.
TESTED on Intel DG43GT with W25Q128.V. With 4 ddr2 dimms time in
raminit goes from 133,857ms (using i2c block read to fetch SPD) to
21,071ms for cached results.
Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This fixes some bitwise logic errors that caused the coarse offset not
to be programmed.
This fixes a regression introduced by 6d7a8c
"nb/intel/x4x/raminit: Rework receive enable calibration"
where the coarse offset doesn't get programmed anymore.
TESTED on Foxconn g41s-k on a DIMM where the final DQS receive enable
delays are close but above and below the edge of a coarse delay setting.
Change-Id: I41869815f782a2ea1178bdea006e3a7587441323
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Moves receive enable calibration to a separate file to lighten
raminit.c a bit.
Receive enable calibration is quite similar to gm45 so it reuses some
of its function names.
The functional changes are:
* the minimum coarse is now reset for each channel;
* on the second fine search for DQS high, TAP overflow is handled by
increasing medium;
* start coarse at CAS + 1 instead of CAS - 1. Other Intel northbridges
do the same and the results are more in line with register dumps
from vendor bios.
These might improve stability.
TESTED on ga-g41m-es2l
Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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