| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-08-10 | src: Fix typo | Elyes HAOUAS |
| 2018-05-24 | nb/intel/x4x: Adapt post JEDEC for DDR3 | Arthur Heymans |
| 2018-05-24 | nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settings | Arthur Heymans |
| 2018-05-24 | nb/intel/x4x: Add DDR3 JEDEC init | Arthur Heymans |
| 2018-04-17 | nb/intel/x4x: Add a convenient macro to loop over bytelanes | Arthur Heymans |
| 2018-04-17 | nb/intel/x4x: Refactor setting default dll settings | Arthur Heymans |
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index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |