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path: root/src/northbridge/intel/x4x/raminit_ddr23.c
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2018-08-04x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
This patch contains the parts that changed the hash of the generated binary; probably due to the compiler optimizing things slightly different. Change-Id: I3233ba1747dcf5ad05b2ad771a86e3936f655d1c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-30x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
When using timeless builds and coreboot crossgcc 6.3.0, the checksum of the resulting binary doesn't change with applying this commit. Change-Id: I057abe314622e92000c7e4ff2faa4595edb5244b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
Some things were coding errors, other things need to be fsb specific. Most things here don't seem to matter all that much but better to get it right. Change-Id: I1afa637a16a083c3a945ba3e2a71292b005736fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
There seems to be a hardware bug where the combination of non-stacked channel settings, both channels populated and 533MHz dram speed cause the display to be unusable. The code to actually select stacked mode based on hardware configuration will be add in a followup patch. This patch does the following: * Add option to the sysinfo struct for stacked mode * Fix programming channel 1 DRB which needs special care for the last populated rank in stacked mode TESTED on Intel dg41wv (with stacked mode hardcoded and dram at 533MHz) Change-Id: I95965bfea129b37f64163159fefa1c8f16331b62 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
Change-Id: I708f98dc2f36af73bb5933d186b4984649e149a1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
Change-Id: I9d34154d3ac1dd1e5400d692d4dcce70d95662c8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans
When programming the final dram attribute and dram boundary settings, on DDR3 dram one also needs to enable ZQCAL in the CxREFRCTRL (DRAM Refresh Control) register as documented in "Intel ® 4 Series Chipset Family" documentation. Change-Id: I11a79f6800dbfe19c2bd33c0d6caca14b034e384 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
DDR3 adapted a fly-by topology which allows for better signal integrity but at the same time requires additional calibration. This is done by settings the targeted rank in write leveling mode while disabling output buffer on the other ranks. After that the DQS signal gets sampled over DQ until a transition from high to low is found. Change-Id: I695969868b4534f87dd1f37244fdfac891a417f0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs) This also modifies the send_jedec_cmd function as DDR3 dimms can have ranks mirrored which needs to be accounted for. The ddr3_emrs1_config array is placed externally since it is also needed for write leveling. Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
Change-Id: Ie32a008ce636b8eee6ed90c364978f7d37f4bfb2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19876 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
Change-Id: Ifef905f5115ffc826b1a355e54c4b1ca818e56fa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19875 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
Adapt the programming of initial DLL values for DDR3. Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: Support programming DDR3 timingsArthur Heymans
Also throws in some minor fixes like the wrong conditional for bankmod and using real CAS when programming MCHBAR(0x248). Change-Id: Ia2494684ec66d84d4dc27c6a6b425a33ace6e827 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-05-14nb/intel/x4x/raminit: Make programming launch ddr3 specificArthur Heymans
Adds nmode to the sysinfo struct as it is needed later on. Change-Id: Ia2ca4a200a1c813b2133eb1004fbe248fa3de9ce Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19872 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x/raminit: Make programming crossclock support DDR3Arthur Heymans
A few values were wrong, but it does not seem to matter all that much. Change-Id: I86b70e06c81817854994b7feddf9f3638fd16198 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19871 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-14nb/intel/x4x: Rename a things that are not specific to DDR2Arthur Heymans
This memory controller supports both DDR2 and DDR3 memory, yet many functions have ddr2 in their name while not being ddr2 specific. This patch renames those to avoid confusion. Change-Id: Ib3d10014f530905155e56fc52706edb4ab9f5630 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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